
#include "userCfgDefault.h"
#include "userProfileLut.h"
#include "bsp_spi.h"

#if 0
#define TEST_WRITE_MEM_ADDR   BB_DBUF0_BASE
#define TEST_READ_MEM_ADDR    BB_DBUF1_BASE

STRUCT_CPX *txpBuf=(STRUCT_CPX *)TEST_WRITE_MEM_ADDR;
void RC8088_ProfileLutPASwitch(uint32_t paNum){
    Write_M8(profMemAddr.txEnMemAddr+0,(1<<paNum)&0xFF);//tx0	
	HAL_RC8088_WrMem(&RC8088_RW, RC8088_CBUFF_BASE,rc8088_userCfg->userMemAddr.cBuf_Addr, 8192>>4);
//	HAL_RC8088_RdMem(&RC8088_RW, RC8088_CBUFF_BASE, (RC8088_MemDat_st *)TEST_READ_MEM_ADDR, (8192)>>4);	    
}
void RC8088_ProfileLutTXPhaseReload(uint32_t frameCnt){
	for(uint32_t i=0;i<128;i++){
		for(uint32_t j=0;j<8;j++){
			txpBuf[i*8+j].txI=i<<1;
			txpBuf[i*8+j].txQ=(frameCnt&0x7F)<<1;
		}
	}
    HAL_RC8088_WrMem(&RC8088_RW, RC8088_TXBUFF_BASE, (RC8088_MemDat_st *)txpBuf, (16*128)>>4);//len:1=16Byte
//	HAL_RC8088_RdMem(&RC8088_RW, RC8088_TXBUFF_BASE, (RC8088_MemDat_st *)TEST_READ_MEM_ADDR, (16*128)>>4);
}
#endif
#if 1
#if AUTO_WAVE_EN 
void RC8088_ProfileLutConfig(RC8088_RWCfg_st *pCfg,RC8088_RegCfg_st *rc8088_regCfg,STRUCT_PROFILEMEM_ADDR *profileMemAddr,STRUCT_RC8088_USERCFG *rc8088_userCfg){
		int rtn;
		uint32_t calcRst;
		STRUCT_PROFILELUT *profileLut=(STRUCT_PROFILELUT *)profileMemAddr->profileAddr;
		STRUCT_CFGCONST *sCfgConst=NULL;
		STRUCT_MEMCONST *sMemConst=NULL;

		if (pCfg->SPI_RF_DEV == RC8088_RF_0)
		{
			sCfgConst=(STRUCT_CFGCONST *)g_rf_far_userconfig.RC8088_ProfileCfgBuf;
			sMemConst=(STRUCT_MEMCONST *)g_rf_far_userconfig.RC8088_ProfileMemBuf;
		}
		else if (pCfg->SPI_RF_DEV == RC8088_RF_1)
		{
			sCfgConst=(STRUCT_CFGCONST *)g_rf_near_userconfig.RC8088_ProfileCfgBuf;
			sMemConst=(STRUCT_MEMCONST *)g_rf_near_userconfig.RC8088_ProfileMemBuf;
		}
		else
		{
			printf("RC8088_ProfileLutConfig pCfg->SPI_RF_DEV err, SPI_RF_DEV is %u.\n", pCfg->SPI_RF_DEV);
			while(1);
		}
		//config memory
		for(uint32_t i=0;i<MAX_PROFILEMEM_NUM;i++){
			//write rampABC
			calcRst=HAL_RC8088_CalcRampReg(sMemConst[i].rampBandwidthA,sMemConst[i].rampTimeA);
			Write_M32(profileMemAddr->rampMemAddr+i*12,calcRst); 
			calcRst=HAL_RC8088_CalcRampReg(sMemConst[i].rampBandwidthB,sMemConst[i].rampTimeB);
            Write_M16(profileMemAddr->rampMemAddr+i*12,calcRst&0xFFFF); 
			Write_M32(profileMemAddr->rampMemAddr+i*12+4,calcRst); 
			calcRst=HAL_RC8088_CalcRampReg(sMemConst[i].rampBandwidthC,sMemConst[i].rampTimeC);
			Write_M32(profileMemAddr->rampMemAddr+i*12+8,calcRst); 
			//write startFreq
			calcRst=HAL_RC8088_CalcStartFreqReg(sMemConst[i].startFreq);
			Write_M32(profileMemAddr->startFreqMemAddr+i*4,calcRst);			
			//write adcRma
			Write_M16(profileMemAddr->adcRmaMemAddr+i*2,sMemConst[i].adcRma);
			//write txEn
			Write_M8(profileMemAddr->txEnMemAddr+i,sMemConst[i].txEn);
			//write txPhase
			Write_M8(profileMemAddr->tx0PhaseMemAddr+i,sMemConst[i].txPhaseIdx[0]);
			Write_M8(profileMemAddr->tx1PhaseMemAddr+i,sMemConst[i].txPhaseIdx[1]);
			Write_M8(profileMemAddr->tx2PhaseMemAddr+i,sMemConst[i].txPhaseIdx[2]);
			Write_M8(profileMemAddr->tx3PhaseMemAddr+i,sMemConst[i].txPhaseIdx[3]);
			Write_M8(profileMemAddr->tx4PhaseMemAddr+i,sMemConst[i].txPhaseIdx[4]);
			Write_M8(profileMemAddr->tx5PhaseMemAddr+i,sMemConst[i].txPhaseIdx[5]);
			Write_M8(profileMemAddr->tx6PhaseMemAddr+i,sMemConst[i].txPhaseIdx[6]);
			Write_M8(profileMemAddr->tx7PhaseMemAddr+i,sMemConst[i].txPhaseIdx[7]);			
		}
		//write bpm
		if (pCfg->SPI_RF_DEV == RC8088_RF_0)
		{
			for(uint32_t i=0;i<MAX_BPM_NUM;i++){
				Write_M8(profileMemAddr->bpmMemAddr+i,g_rf_far_userconfig.RC8088_BpmBuf[i]);
			}
		}
		else if (pCfg->SPI_RF_DEV == RC8088_RF_1)
		{
			for(uint32_t i=0;i<MAX_BPM_NUM;i++){
				Write_M8(profileMemAddr->bpmMemAddr+i,g_rf_near_userconfig.RC8088_BpmBuf[i]);
			}
		}
		else
		{
			printf("RC8088_ProfileLutConfig pCfg->SPI_RF_DEV err, SPI_RF_DEV is %u.\n", pCfg->SPI_RF_DEV);
			while(1);
		}
		for(uint32_t sCnt=0;sCnt<MAX_PROFILE_NUM;sCnt++){
			profileLut[sCnt].waveCfg0=(0<<12)| //ramp_rma
															  (1<<10)| //A_PLLACC
															  (1<<9)|  //B_PLLACC
															  (1<<8)|  //C_PLLACC
															  (sCfgConst[sCnt].rampPA_En<<4)|  //ABC_PAenable
														    (sCfgConst[sCnt].rampSYNC_En<<0);  //ABC_SYNCenable
			profileLut[sCnt].waveCfg1=(0<<4)|  //interProfileIdleTimeScaleB
														    (0);     //interProfileIdleTimeValueB
			profileLut[sCnt].waveCfg2=(0<<7)|  //loopInf
														    (1-1);   //loopNum[6:0]
			profileLut[sCnt].powerCfg0 = rc8088_regCfg->ANA.CFG00.WORD; //run:1
			profileLut[sCnt].powerCfg1 = rc8088_regCfg->ANA.CFG00.WORD; //idle:0
			profileLut[sCnt].anaCfg0=rc8088_regCfg->ANA.CFG01.WORD;
			profileLut[sCnt].anaCfg1=rc8088_regCfg->ANA.CFG02.WORD;
			profileLut[sCnt].anaCfg2=rc8088_regCfg->ANA.CFG03.WORD;
			profileLut[sCnt].anaCfg3=rc8088_regCfg->ANA.CFG04.WORD;
			profileLut[sCnt].anaCfg4=rc8088_regCfg->ANA.CFG05.WORD;
			profileLut[sCnt].anaCfg5=rc8088_regCfg->ANA.CFG06.WORD;
			//profile lut ramp
			profileLut[sCnt].lutRampCfg0=(sCfgConst[sCnt].rampMemIncHP<<24)|          //rampInterInc[7:0]
																(sCfgConst[sCnt].rampMemIncLP<<16)|          //rampIntraInc[3:0]
																((profileMemAddr->rampMemAddr-profileMemAddr->profileAddr+12*sCfgConst[sCnt].rampMemAddr)&0xFFFF);  //rampBaseAddr[15:0]     offset,byte
			profileLut[sCnt].lutRampCfg1=((sCfgConst[sCnt].rampCountHP)<<8)|   //rampInterCnt[7:0]
															  (sCfgConst[sCnt].rampCountLP);      //rampIntraCnt[7:0]
			profileLut[sCnt].lutRampCfg2=(0<<16)|//deltaInterInc_ramp_a_time
																(0);    //deltaInterInc_ramp_a_inc
			profileLut[sCnt].lutRampCfg3=(0<<16)|//deltaInterInc_ramp_b_time
																(0);    //deltaInterInc_ramp_b_inc
			profileLut[sCnt].lutRampCfg4=(0<<16)|//deltaInterInc_ramp_c_time
																(0);    //deltaInterInc_ramp_c_inc
			profileLut[sCnt].lutRampCfg5=(0<<16)|//deltaIntraInc_ramp_a_time
																(0);    //deltaIntraInc_ramp_a_inc
			profileLut[sCnt].lutRampCfg6=(0<<16)|//deltaIntraInc_ramp_b_time
																(0);    //deltaIntraInc_ramp_b_inc
			profileLut[sCnt].lutRampCfg7=(0<<16)|//deltaIntraInc_ramp_c_time
																(0);    //deltaIntraInc_ramp_c_inc
			//profile lut startFreq
			profileLut[sCnt].lutStartFreqCfg0=(0<<24)|           //startFreqInterInc[7:0]
																		 (0<<16)|           //startFreqIntraInc[3:0]
																		 ((profileMemAddr->startFreqMemAddr-profileMemAddr->profileAddr+4*sCfgConst[sCnt].startFreqMemAddr)&0xFFFF); //startFreqBaseAddr[15:0]
//			float tempVal1= (float)rc8088_userCfg->startFreqStep1Val*1000.0f/1.5f;
//			float tempVal2= (float)rc8088_userCfg->startFreqStep2Val*1000.0f/1.5f;
			profileLut[sCnt].lutStartFreqCfg1=((sCfgConst[sCnt].startFreqCountHP)<<8)|            //startFreqInterCnt[7:0]
																		 (sCfgConst[sCnt].startFreqCountLP);                 //startFreqIntraCnt[7:0]
			profileLut[sCnt].lutStartFreqCfg2=sCfgConst[sCnt].startFreqStepIncHP;                 //deltaInterInc_startFreq
			profileLut[sCnt].lutStartFreqCfg3=sCfgConst[sCnt].startFreqStepIncLP;                 //deltaIntraInc_startFreq 1=1.5K
			//profile lut adcRma
			profileLut[sCnt].lutAdcRmaCfg0=(0<<24)|              //adcRmaInterInc[7:0]
																	(0<<16)|              //adcRmaIntraInc[3:0]
																	((profileMemAddr->adcRmaMemAddr-profileMemAddr->profileAddr+2*sCfgConst[sCnt].adcRmaMemAddr)&0xFFFF);    //adcRmaBaseAddr[15:0]
			profileLut[sCnt].lutAdcRmaCfg1=(0<<8)|               //adcRmaInterCnt[7:0]
																	(0);                  //adcRmaIntraCnt[7:0]
			profileLut[sCnt].lutAdcRmaCfg2=(0<<16)|              //deltaInterInc_adcRma
																	(0);                  //deltaIntraInc_adcRma
			//profile lut txEn
			profileLut[sCnt].lutTxEnCfg0=(0<<24)|                //txEnInterInc[7:0]
																(sCfgConst[sCnt].txEnMemInc<<16)|                //txEnIntraInc[3:0]
																((profileMemAddr->txEnMemAddr-profileMemAddr->profileAddr+sCfgConst[sCnt].txEnMemAddr)&0xFFFF);      //txEnBaseAddr[15:0]
			profileLut[sCnt].lutTxEnCfg1=(0<<8)|                 											//txEnInterCnt[7:0]
																(sCfgConst[sCnt].txEnCount);                    //txEnIntraCnt[7:0]
			//profile lut bpm
			profileLut[sCnt].lutBpmCfg0=(0<<24)|                 //bpmInterInc[7:0]
															 (sCfgConst[sCnt].bpmMemInc<<16)|                 //bpmIntraInc[3:0]
															 ((profileMemAddr->bpmMemAddr-profileMemAddr->profileAddr)&0xFFFF);       //bpmBaseAddr[15:0]
			profileLut[sCnt].lutBpmCfg1=(0<<8)|                  //bpmInterCnt[7:0]
															 (sCfgConst[sCnt].bpmCount);                     //bpmIntraCnt[7:0]
			//profile lut tx0 phase
			profileLut[sCnt].lutTx0PhaseCfg0=(0<<24)|(sCfgConst[sCnt].txPhaseMemInc[0]<<16)|((profileMemAddr->tx0PhaseMemAddr-profileMemAddr->profileAddr+sCfgConst[sCnt].txPhaseMemAddr[0])&0xFFFF);//interInc,intraInc,baseAddr
			profileLut[sCnt].lutTx0PhaseCfg1=(0<<24)|(sCfgConst[sCnt].txPhaseStepInc[0]<<16)|(0<<8)|(sCfgConst[sCnt].txPhaseCount[0]);//deltaInterInc,deltaIntraInc,interCnt,intraCnt
			//profile lut tx1 phase
			profileLut[sCnt].lutTx1PhaseCfg0=(0<<24)|(sCfgConst[sCnt].txPhaseMemInc[1]<<16)|((profileMemAddr->tx1PhaseMemAddr-profileMemAddr->profileAddr+sCfgConst[sCnt].txPhaseMemAddr[1])&0xFFFF);//interInc,intraInc,baseAddr
			profileLut[sCnt].lutTx1PhaseCfg1=(0<<24)|(sCfgConst[sCnt].txPhaseStepInc[1]<<16)|(0<<8)|(sCfgConst[sCnt].txPhaseCount[1]);//deltaInterInc,deltaIntraInc,interCnt,intraCnt
			//profile lut tx2 phase
			profileLut[sCnt].lutTx2PhaseCfg0=(0<<24)|(sCfgConst[sCnt].txPhaseMemInc[2]<<16)|((profileMemAddr->tx2PhaseMemAddr-profileMemAddr->profileAddr+sCfgConst[sCnt].txPhaseMemAddr[2])&0xFFFF);//interInc,intraInc,baseAddr
			profileLut[sCnt].lutTx2PhaseCfg1=(0<<24)|(sCfgConst[sCnt].txPhaseStepInc[2]<<16)|(0<<8)|(sCfgConst[sCnt].txPhaseCount[2]);//deltaInterInc,deltaIntraInc,interCnt,intraCnt
			//profile lut tx3 phase
			profileLut[sCnt].lutTx3PhaseCfg0=(0<<24)|(sCfgConst[sCnt].txPhaseMemInc[3]<<16)|((profileMemAddr->tx3PhaseMemAddr-profileMemAddr->profileAddr+sCfgConst[sCnt].txPhaseMemAddr[3])&0xFFFF);//interInc,intraInc,baseAddr
			profileLut[sCnt].lutTx3PhaseCfg1=(0<<24)|(sCfgConst[sCnt].txPhaseStepInc[3]<<16)|(0<<8)|(sCfgConst[sCnt].txPhaseCount[3]);//deltaInterInc,deltaIntraInc,interCnt,intraCnt
			//profile lut tx4 phase
			profileLut[sCnt].lutTx4PhaseCfg0=(0<<24)|(sCfgConst[sCnt].txPhaseMemInc[4]<<16)|((profileMemAddr->tx4PhaseMemAddr-profileMemAddr->profileAddr+sCfgConst[sCnt].txPhaseMemAddr[4])&0xFFFF);//interInc,intraInc,baseAddr
			profileLut[sCnt].lutTx4PhaseCfg1=(0<<24)|(sCfgConst[sCnt].txPhaseStepInc[4]<<16)|(0<<8)|(sCfgConst[sCnt].txPhaseCount[4]);//deltaInterInc,deltaIntraInc,interCnt,intraCnt
			//profile lut tx5 phase
			profileLut[sCnt].lutTx5PhaseCfg0=(0<<24)|(sCfgConst[sCnt].txPhaseMemInc[5]<<16)|((profileMemAddr->tx5PhaseMemAddr-profileMemAddr->profileAddr+sCfgConst[sCnt].txPhaseMemAddr[5])&0xFFFF);//interInc,intraInc,baseAddr
			profileLut[sCnt].lutTx5PhaseCfg1=(0<<24)|(sCfgConst[sCnt].txPhaseStepInc[5]<<16)|(0<<8)|(sCfgConst[sCnt].txPhaseCount[5]);//deltaInterInc,deltaIntraInc,interCnt,intraCnt
			//profile lut tx6 phase
			profileLut[sCnt].lutTx6PhaseCfg0=(0<<24)|(sCfgConst[sCnt].txPhaseMemInc[6]<<16)|((profileMemAddr->tx6PhaseMemAddr-profileMemAddr->profileAddr+sCfgConst[sCnt].txPhaseMemAddr[6])&0xFFFF);//interInc,intraInc,baseAddr
			profileLut[sCnt].lutTx6PhaseCfg1=(0<<24)|(sCfgConst[sCnt].txPhaseStepInc[6]<<16)|(0<<8)|(sCfgConst[sCnt].txPhaseCount[6]);//deltaInterInc,deltaIntraInc,interCnt,intraCnt
			//profile lut tx7 phase
			profileLut[sCnt].lutTx7PhaseCfg0=(0<<24)|(sCfgConst[sCnt].txPhaseMemInc[7]<<16)|((profileMemAddr->tx7PhaseMemAddr-profileMemAddr->profileAddr+sCfgConst[sCnt].txPhaseMemAddr[7])&0xFFFF);//interInc,intraInc,baseAddr
			profileLut[sCnt].lutTx7PhaseCfg1=(0<<24)|(sCfgConst[sCnt].txPhaseStepInc[7]<<16)|(0<<8)|(sCfgConst[sCnt].txPhaseCount[7]);//deltaInterInc,deltaIntraInc,interCnt,intraCnt
		}
		rtn = HAL_RC8088_WrMem(pCfg, RC8088_CBUFF_BASE,rc8088_userCfg->userMemAddr.cBuf_Addr, 8192>>4);
		printf("RC8088_CBUFF_BASE write  err:%d\n",rtn);
		if (pCfg->SPI_RF_DEV == RC8088_RF_0)
		{
			rtn =HAL_RC8088_WrMem(pCfg, RC8088_TXBUFF_BASE, (RC8088_MemDat_st *)g_rf_far_userconfig.RC8088_TxpBuf, (16*128)>>4);//len:1=16Byte
			printf("RC8088_TXBUFF_BASE write  err:%d\n",rtn);
		}
		else if (pCfg->SPI_RF_DEV == RC8088_RF_1)
		{
			rtn =HAL_RC8088_WrMem(pCfg, RC8088_TXBUFF_BASE, (RC8088_MemDat_st *)g_rf_near_userconfig.RC8088_TxpBuf, (16*128)>>4);//len:1=16Byte
			printf("RC8088_TXBUFF_BASE write  err:%d\n",rtn);
		}
		else
		{
			printf("RC8088_ProfileLutConfig pCfg->SPI_RF_DEV err, SPI_RF_DEV is %u.\n", pCfg->SPI_RF_DEV);
			while(1);
		}
}

#endif

#endif

#if TEST_COMPELX_WAVE_EN
/*
	QT need to config list :
	prep:numPT=1024
	profileMan:numChirp=2048
	startFreq=78G
	bandwidth=4G
	MIPI: laneSpeed=800M
*/
const uint16_t txpBuf_Idx0_127[]={ //F2-TX8
		17934,15382,14880,11808,13354,10796,9260,9268,6196,9282,824,8270,8788,4698,2652,1118,614,2158,2164,5240,3710,2182,4748,2192,2198,2206,3744,5790,3754,2738,7852,6324,8886,5316,7872,9412,8908,8916,14026,13522,15058,13538,17116,16098,16106,19682,20706,20724,23276,24804,25836,26354,27386,29432,29932,31482,34542,33526,36078,37622,39162,39666,43762,44272,44782,44770,46310,48344,51430,50396,50388,54482,56020,55494,56004,59590,59582,60598,59568,58534,57506,60062,59546,63640,63630,65164,64648,63102,65142,65136,62572,58986,62050,63068,62548,59984,59980,56906,59966,56386,57906,54836,56364,54820,51758,51748,50724,49694,45606,45086,44572,43040,42000,40978,39440,38926,36366,34836,32268,31232,29192,27652,27150,24590,23572,22542,19990,18450
};
const uint8_t testBmpBuff[]={
0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150,0,170,204,102,240,90,60,150
};
void RC8088_ProfileLutComplexWaveConfig(void){
	STRUCT_PROFILELUT *profileWave=(STRUCT_PROFILELUT *)profMemAddr.profileAddr;
	//write cbuf
	#if 1 //const
		for (uint32_t j=0;j<128;j++){
			for(uint32_t i=0;i<8;i++){
				Write_M16(TEST_WRITE_MEM_ADDR+i*2+j*16,txpBuf_Idx0_127[j]);
			}
		}
		HAL_RC8088_WrMem(&RC8088_RW, RC8088_TXBUFF_BASE, (RC8088_MemDat_st *)TEST_WRITE_MEM_ADDR, (16*128)>>4);//len:1=16Byte
		HAL_RC8088_RdMem(&RC8088_RW, RC8088_TXBUFF_BASE, (RC8088_MemDat_st *)TEST_READ_MEM_ADDR, (16*128)>>4);
	#endif
	//config init
	rc8088_userCfg->numProf = 28;
	rc8088_userCfg->adcRmaInitVal=250;
	rc8088_regCfg->PROFILE_MAN.ProfileMan_CFG0.BIT.profile_man_vld=0;
	HAL_RC8088_WrReg(&RC8088_RW, &rc8088_regCfg->PROFILE_MAN.ProfileMan_CFG0, 1);
	//subframe
    #if 1
	rc8088_regCfg->SF.SF_CFG0.BIT.sf0_profileLoopInf          =0;
	rc8088_regCfg->SF.SF_CFG0.BIT.sf0_profileLoopNum          =6-1;
	rc8088_regCfg->SF.SF_CFG0.BIT.sf0_profileNumA             =0;
	rc8088_regCfg->SF.SF_CFG0.BIT.sf0_profileNumB             =1;
	rc8088_regCfg->SF.SF_CFG0.BIT.sf0_interFrameIdleTimeScaleB=3;
	rc8088_regCfg->SF.SF_CFG0.BIT.sf0_interFrameIdleTimeValueB=8;
    #endif
    #if 0
	rc8088_regCfg->SF.SF_CFG0.BIT.sf0_profileLoopInf          =0;
	rc8088_regCfg->SF.SF_CFG0.BIT.sf0_profileLoopNum          =2-1;
	rc8088_regCfg->SF.SF_CFG0.BIT.sf0_profileNumA             =2;
	rc8088_regCfg->SF.SF_CFG0.BIT.sf0_profileNumB             =7;
	rc8088_regCfg->SF.SF_CFG0.BIT.sf0_interFrameIdleTimeScaleB=3;
	rc8088_regCfg->SF.SF_CFG0.BIT.sf0_interFrameIdleTimeValueB=9;
    #endif
    #if 0
	rc8088_regCfg->SF.SF_CFG0.BIT.sf0_profileLoopInf          =0;
	rc8088_regCfg->SF.SF_CFG0.BIT.sf0_profileLoopNum          =6-1;
	rc8088_regCfg->SF.SF_CFG0.BIT.sf0_profileNumA             =8;
	rc8088_regCfg->SF.SF_CFG0.BIT.sf0_profileNumB             =9;
	rc8088_regCfg->SF.SF_CFG0.BIT.sf0_interFrameIdleTimeScaleB=3;
	rc8088_regCfg->SF.SF_CFG0.BIT.sf0_interFrameIdleTimeValueB=10;
    #endif
    #if 0
	rc8088_regCfg->SF.SF_CFG0.BIT.sf0_profileLoopInf          =0;
	rc8088_regCfg->SF.SF_CFG0.BIT.sf0_profileLoopNum          =1-1;
	rc8088_regCfg->SF.SF_CFG0.BIT.sf0_profileNumA             =10;
	rc8088_regCfg->SF.SF_CFG0.BIT.sf0_profileNumB             =27;
	rc8088_regCfg->SF.SF_CFG0.BIT.sf0_interFrameIdleTimeScaleB=3;
	rc8088_regCfg->SF.SF_CFG0.BIT.sf0_interFrameIdleTimeValueB=11;
    #endif
	HAL_RC8088_WrReg(&RC8088_RW, &rc8088_regCfg->SF.SF_CFG0, 1);
	rc8088_regCfg->SF.SF_CFG1.BIT.sf1_valid                   =0;
	rc8088_regCfg->SF.SF_CFG1.BIT.sf1_profileLoopInf          =0;
	rc8088_regCfg->SF.SF_CFG1.BIT.sf1_profileLoopNum          =2-1;
	rc8088_regCfg->SF.SF_CFG1.BIT.sf1_profileNumA             =2;
	rc8088_regCfg->SF.SF_CFG1.BIT.sf1_profileNumB             =7;
	rc8088_regCfg->SF.SF_CFG1.BIT.sf1_interFrameIdleTimeScaleB=3;
	rc8088_regCfg->SF.SF_CFG1.BIT.sf1_interFrameIdleTimeValueB=9;
	HAL_RC8088_WrReg(&RC8088_RW, &rc8088_regCfg->SF.SF_CFG1, 1);	
	rc8088_regCfg->SF.SF_CFG2.BIT.sf2_valid                   =0;
	rc8088_regCfg->SF.SF_CFG2.BIT.sf2_profileLoopInf          =0;
	rc8088_regCfg->SF.SF_CFG2.BIT.sf2_profileLoopNum          =6-1;
	rc8088_regCfg->SF.SF_CFG2.BIT.sf2_profileNumA             =8;
	rc8088_regCfg->SF.SF_CFG2.BIT.sf2_profileNumB             =9;
	rc8088_regCfg->SF.SF_CFG2.BIT.sf2_interFrameIdleTimeScaleB=3;
	rc8088_regCfg->SF.SF_CFG2.BIT.sf2_interFrameIdleTimeValueB=10;
	HAL_RC8088_WrReg(&RC8088_RW, &rc8088_regCfg->SF.SF_CFG2, 1);	
	rc8088_regCfg->SF.SF_CFG3.BIT.sf3_valid                   =0;
	rc8088_regCfg->SF.SF_CFG3.BIT.sf3_profileLoopInf          =0;
	rc8088_regCfg->SF.SF_CFG3.BIT.sf3_profileLoopNum          =1-1;
	rc8088_regCfg->SF.SF_CFG3.BIT.sf3_profileNumA             =10;
	rc8088_regCfg->SF.SF_CFG3.BIT.sf3_profileNumB             =27;
	rc8088_regCfg->SF.SF_CFG3.BIT.sf3_interFrameIdleTimeScaleB=3;
	rc8088_regCfg->SF.SF_CFG3.BIT.sf3_interFrameIdleTimeValueB=11;
	HAL_RC8088_WrReg(&RC8088_RW, &rc8088_regCfg->SF.SF_CFG3, 1);	
	
	//write profile addr
  for (uint32_t sCnt=0;sCnt<rc8088_userCfg->numProf;sCnt++){
		profileWave[sCnt].waveCfg0=(0<<12)| //ramp_rma
								   (0<<10)| //A_PLLACC
								   (0<<9)|  //B_PLLACC
								   (0<<8)|  //C_PLLACC
								   (1<<6)|  //A_PAenable
								   (1<<5)|  //B_PAenable
								   (0<<4)|  //C_PAenable
								   (1<<2)|  //ramp_sync_maskA
								   (0<<1)|  //ramp_sync_maskB
								   (0);     //ramp_sync_maskC
		profileWave[sCnt].waveCfg1=(0<<4)|  //interProfileIdleTimeScaleB
								   (0);     //interProfileIdleTimeValueB
		profileWave[sCnt].waveCfg2=(0<<7)|  //loopInf
								   (1-1);  //loopNum[6:0]
		profileWave[sCnt].powerCfg0 = rc8088_regCfg->ANA.CFG00.WORD; //run:1
		profileWave[sCnt].powerCfg1 = rc8088_regCfg->ANA.CFG00.WORD; //idle:0
		profileWave[sCnt].anaCfg0=rc8088_regCfg->ANA.CFG01.WORD;
		profileWave[sCnt].anaCfg1=rc8088_regCfg->ANA.CFG02.WORD;
		profileWave[sCnt].anaCfg2=rc8088_regCfg->ANA.CFG03.WORD;
		profileWave[sCnt].anaCfg3=rc8088_regCfg->ANA.CFG04.WORD;
		profileWave[sCnt].anaCfg4=rc8088_regCfg->ANA.CFG05.WORD;
		profileWave[sCnt].anaCfg5=rc8088_regCfg->ANA.CFG06.WORD;
		//profile lut ramp
		profileWave[sCnt].lutRampCfg0=(0<<24)|          //rampInterInc[7:0]
									  (0<<16)|          //rampIntraInc[3:0]
									  ((profMemAddr.rampMemAddr-profMemAddr.profileAddr+0x20)&0xFFFF);  //rampBaseAddr[15:0]     offset,byte
		profileWave[sCnt].lutRampCfg1=((32-1)<<8)|           //rampInterCnt[7:0]
									  (64-1);      //rampIntraCnt[7:0]
		profileWave[sCnt].lutRampCfg2=(0<<16)|          //deltaInterInc_ramp_a_time
									  (0);              //deltaInterInc_ramp_a_inc
		profileWave[sCnt].lutRampCfg3=(0<<16)|          //deltaInterInc_ramp_b_time
									  (0);              //deltaInterInc_ramp_b_inc
		profileWave[sCnt].lutRampCfg4=(0<<16)|          //deltaInterInc_ramp_c_time
									  (0);              //deltaInterInc_ramp_c_inc
		profileWave[sCnt].lutRampCfg5=(0<<16)|          //deltaIntraInc_ramp_a_time
									  (0);              //deltaIntraInc_ramp_a_inc
		profileWave[sCnt].lutRampCfg6=(0<<16)|          //deltaIntraInc_ramp_b_time
									  (0);              //deltaIntraInc_ramp_b_inc
		profileWave[sCnt].lutRampCfg7=(0<<16)|          //deltaIntraInc_ramp_c_time
									  (0);              //deltaIntraInc_ramp_c_inc
		//profile lut startFreq
		profileWave[sCnt].lutStartFreqCfg0=(0<<24)|           //startFreqInterInc[7:0]
										   (0<<16)|           //startFreqIntraInc[3:0]
										   ((profMemAddr.startFreqMemAddr-profMemAddr.profileAddr)&0xFFFF); //startFreqBaseAddr[15:0]
		profileWave[sCnt].lutStartFreqCfg1=(0<<8)|            //startFreqInterCnt[7:0]
										   (0);               //startFreqIntraCnt[7:0]
		profileWave[sCnt].lutStartFreqCfg2=0;                 //deltaInterInc_startFreq
		profileWave[sCnt].lutStartFreqCfg3=0;                 //deltaIntraInc_startFreq
		//profile lut adcRma
		profileWave[sCnt].lutAdcRmaCfg0=(0<<24)|              //adcRmaInterInc[7:0]
										(0<<16)|              //adcRmaIntraInc[3:0]
										((profMemAddr.adcRmaMemAddr-profMemAddr.profileAddr)&0xFFFF);    //adcRmaBaseAddr[15:0]
		profileWave[sCnt].lutAdcRmaCfg1=(0<<8)|               //adcRmaInterCnt[7:0]
										(0);                  //adcRmaIntraCnt[7:0]
		profileWave[sCnt].lutAdcRmaCfg2=(0<<16)|              //deltaInterInc_adcRma
										(0);                  //deltaIntraInc_adcRma
		//profile lut txEn
		profileWave[sCnt].lutTxEnCfg0=(0<<24)|                //txEnInterInc[7:0]
									  (0<<16)|                //txEnIntraInc[3:0]
									  ((profMemAddr.txEnMemAddr-profMemAddr.profileAddr)&0xFFFF);      //txEnBaseAddr[15:0]
		profileWave[sCnt].lutTxEnCfg1=(0<<8)|                 //txEnInterCnt[7:0]
									  (0);                    //txEnIntraCnt[7:0]
		//profile lut bpm
		profileWave[sCnt].lutBpmCfg0=(0<<24)|                 //bpmInterInc[7:0]
									 (0<<16)|                 //bpmIntraInc[3:0]
									 ((profMemAddr.bpmMemAddr-profMemAddr.profileAddr)&0xFFFF);       //bpmBaseAddr[15:0]
		profileWave[sCnt].lutBpmCfg1=(0<<8)|                  //bpmInterCnt[7:0]
									 (0);                     //bpmIntraCnt[7:0]
		//profile lut tx0 phase
		profileWave[sCnt].lutTx0PhaseCfg0=(0<<24)|(0<<16)|((profMemAddr.tx0PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);
		profileWave[sCnt].lutTx0PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(1-1);
		//profile lut tx1 phase
		profileWave[sCnt].lutTx1PhaseCfg0=(0<<24)|(0<<16)|((profMemAddr.tx0PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);
		profileWave[sCnt].lutTx1PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(1-1);
		//profile lut tx2 phase
		profileWave[sCnt].lutTx2PhaseCfg0=(0<<24)|(0<<16)|((profMemAddr.tx0PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);
		profileWave[sCnt].lutTx2PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(1-1);
		//profile lut tx3 phase
		profileWave[sCnt].lutTx3PhaseCfg0=(0<<24)|(0<<16)|((profMemAddr.tx0PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);
		profileWave[sCnt].lutTx3PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(1-1);
		//profile lut tx4 phase
		profileWave[sCnt].lutTx4PhaseCfg0=(0<<24)|(0<<16)|((profMemAddr.tx0PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);
		profileWave[sCnt].lutTx4PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(1-1);
		//profile lut tx5 phase
		profileWave[sCnt].lutTx5PhaseCfg0=(0<<24)|(0<<16)|((profMemAddr.tx0PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);
		profileWave[sCnt].lutTx5PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(1-1);
		//profile lut tx6 phase
		profileWave[sCnt].lutTx6PhaseCfg0=(0<<24)|(0<<16)|((profMemAddr.tx0PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);
		profileWave[sCnt].lutTx6PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(1-1);
		//profile lut tx7 phase
		profileWave[sCnt].lutTx7PhaseCfg0=(0<<24)|(0<<16)|((profMemAddr.tx0PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);
		profileWave[sCnt].lutTx7PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(1-1);
	}
    /*write memory*/
    //ramp ABC
    uint32_t rampRst=0;
    /*1000+1000+1000 0G*/
    Write_M32(profMemAddr.rampMemAddr+0x00,(uint32_t)(40*1000)<<16|((0)&0xFFFF)); //1000us
    Write_M32(profMemAddr.rampMemAddr+0x04,(uint32_t)(40*1000)<<16|((0)&0xFFFF)); //1000us
    Write_M32(profMemAddr.rampMemAddr+0x08,(uint32_t)(40*1000)<<16|((0)&0xFFFF)); //1000us
    /*10+25+50 2G*/
    rampRst=HAL_RC8088_CalcRampReg(2,25);
    Write_M32(profMemAddr.rampMemAddr+0x0C,(40*10)<<16|((0)&0xFFFF)); //10us
//    Write_M32(PROFILE_BASE+RAMPABC_MEM_OFFSET+0x10,(40*20)<<16|((0)&0xFFFF)); //20us@0G
    Write_M32(profMemAddr.rampMemAddr+0x10,(rampRst<<16)|((rampRst>>16)&0xFFFF)); //25us@2G
//    Write_M32(PROFILE_BASE+RAMPABC_MEM_OFFSET+0x10,(40*20)<<16|((0x033A)&0xFFFF)); //20us@1G
//    Write_M32(PROFILE_BASE+RAMPABC_MEM_OFFSET+0x10,(40*20)<<16|((0x019D)&0xFFFF)); //20us@0.5G
    Write_M32(profMemAddr.rampMemAddr+0x14,(40*50)<<16|((0)&0xFFFF)); //20us
    /*10+25+50 2G*/
    rampRst=HAL_RC8088_CalcRampReg(2,25);
    Write_M32(profMemAddr.rampMemAddr+0x20,(40*10)<<16|((0)&0xFFFF)); //10us
//    Write_M32(PROFILE_BASE+RAMPABC_MEM_OFFSET+0x24,(40*20)<<16|((0)&0xFFFF)); //20us@0G
    Write_M32(profMemAddr.rampMemAddr+0x24,(rampRst<<16)|((rampRst>>16)&0xFFFF)); //25us@2G
//    Write_M32(PROFILE_BASE+RAMPABC_MEM_OFFSET+0x24,(40*20)<<16|((0x033A)&0xFFFF)); //20us@1G
//    Write_M32(PROFILE_BASE+RAMPABC_MEM_OFFSET+0x24,(40*20)<<16|((0x019D)&0xFFFF)); //20us@0.5G
    Write_M32(profMemAddr.rampMemAddr+0x28,(40*50)<<16|((0)&0xFFFF)); //20us
    /*10+25+50 0G*/
    Write_M32(profMemAddr.rampMemAddr+0x30,(40*10)<<16|((0)&0xFFFF)); //10us
    Write_M32(profMemAddr.rampMemAddr+0x34,(40*25)<<16|((0)&0xFFFF)); //20us@0G
    Write_M32(profMemAddr.rampMemAddr+0x38,(40*50)<<16|((0)&0xFFFF)); //20us
    /*10+25+50 1G*/
    rampRst=HAL_RC8088_CalcRampReg(1,25);
    Write_M32(profMemAddr.rampMemAddr+0x40,(40*10)<<16|((0)&0xFFFF)); //10us
    Write_M32(profMemAddr.rampMemAddr+0x44,(rampRst<<16)|((rampRst>>16)&0xFFFF)); //25us@1G
    Write_M32(profMemAddr.rampMemAddr+0x48,(40*50)<<16|((0)&0xFFFF)); //20us
    //startFreq
    Write_M32(profMemAddr.startFreqMemAddr,0x00BCBCA1); //start freq  : 78G:0x00BCBCA1
//    Write_M32(profMemAddr.startFreqMemAddr+4,0x0103B5E5); //start freq  : 76.5G:0x0103B5E5 77G:0x0108C11F 78G:0x0112D794
    //adcRma
    Write_M16(profMemAddr.adcRmaMemAddr+0,rc8088_userCfg->adcRmaInitVal);
    Write_M16(profMemAddr.adcRmaMemAddr+2,rc8088_userCfg->adcRmaInitVal);
    Write_M16(profMemAddr.adcRmaMemAddr+4,rc8088_userCfg->adcRmaInitVal);
    Write_M16(profMemAddr.adcRmaMemAddr+6,rc8088_userCfg->adcRmaInitVal);
    Write_M16(profMemAddr.adcRmaMemAddr+8,500);
    Write_M16(profMemAddr.adcRmaMemAddr+10,500);
    Write_M16(profMemAddr.adcRmaMemAddr+12,500);
    Write_M16(profMemAddr.adcRmaMemAddr+14,500);
    //txEn
    /*tx0,1,2,3,4*/
    Write_M8(profMemAddr.txEnMemAddr+0,0x01);//tx0
    Write_M8(profMemAddr.txEnMemAddr+1,0x02);//tx1
    Write_M8(profMemAddr.txEnMemAddr+2,0x04);//tx2
    Write_M8(profMemAddr.txEnMemAddr+3,0x08);//tx3
    Write_M8(profMemAddr.txEnMemAddr+4,0x10);//tx4
    /*tx5,6,7*/
    Write_M8(profMemAddr.txEnMemAddr+0x10+0,0x20);//tx5
    Write_M8(profMemAddr.txEnMemAddr+0x10+1,0x40);//tx6
    Write_M8(profMemAddr.txEnMemAddr+0x10+2,0x80);//tx7
    /*tx0,1,2,3,4,5,6,7*/
    Write_M8(profMemAddr.txEnMemAddr+0x20+0,0x01);//tx0
    Write_M8(profMemAddr.txEnMemAddr+0x20+1,0x02);//tx1
    Write_M8(profMemAddr.txEnMemAddr+0x20+2,0x04);//tx2
    Write_M8(profMemAddr.txEnMemAddr+0x20+3,0x08);//tx3
    Write_M8(profMemAddr.txEnMemAddr+0x20+4,0x10);//tx4
    Write_M8(profMemAddr.txEnMemAddr+0x20+5,0x20);//tx5
    Write_M8(profMemAddr.txEnMemAddr+0x20+6,0x40);//tx6
    Write_M8(profMemAddr.txEnMemAddr+0x20+7,0x80);//tx7

//    Write_M8(profMemAddr.txEnMemAddr+0x20+0,0x00);//tx0
//    Write_M8(profMemAddr.txEnMemAddr+0x20+1,0x00);//tx1
//    Write_M8(profMemAddr.txEnMemAddr+0x20+2,0x00);//tx2
//    Write_M8(profMemAddr.txEnMemAddr+0x20+3,0x00);//tx3
//    Write_M8(profMemAddr.txEnMemAddr+0x20+4,0x00);//tx4
//    Write_M8(profMemAddr.txEnMemAddr+0x20+5,0x00);//tx5
//    Write_M8(profMemAddr.txEnMemAddr+0x20+6,0x00);//tx6
//    Write_M8(profMemAddr.txEnMemAddr+0x20+7,0x00);//tx7
    /*tx0-6,1-7,0-3*/
    Write_M8(profMemAddr.txEnMemAddr+0x30+0,0x7F);//tx0-6
    Write_M8(profMemAddr.txEnMemAddr+0x40+0,0xFE);//tx1-7
    Write_M8(profMemAddr.txEnMemAddr+0x50+0,0x0F);//tx0-3
    //bpm
    for(uint32_t i=0;i<2050;i++){
    	Write_M8(profMemAddr.bpmMemAddr+i,testBmpBuff[i]);//bpm
    }
    //txPhase
	Write_M8 (profMemAddr.tx0PhaseMemAddr+0,0);
	Write_M8 (profMemAddr.tx0PhaseMemAddr+1,43);
	Write_M8 (profMemAddr.tx0PhaseMemAddr+2,85);

	Write_M8 (profMemAddr.tx1PhaseMemAddr+0,0);
	Write_M8 (profMemAddr.tx1PhaseMemAddr+1,32);
	Write_M8 (profMemAddr.tx1PhaseMemAddr+2,64);
	Write_M8 (profMemAddr.tx1PhaseMemAddr+3,96);

	Write_M8 (profMemAddr.tx2PhaseMemAddr+0,0);
	Write_M8 (profMemAddr.tx2PhaseMemAddr+1,26);
	Write_M8 (profMemAddr.tx2PhaseMemAddr+2,51);
	Write_M8 (profMemAddr.tx2PhaseMemAddr+3,77);
	Write_M8 (profMemAddr.tx2PhaseMemAddr+4,102);

	Write_M8 (profMemAddr.tx3PhaseMemAddr+0,0);
	Write_M8 (profMemAddr.tx3PhaseMemAddr+1,18);
	Write_M8 (profMemAddr.tx3PhaseMemAddr+2,37);
	Write_M8 (profMemAddr.tx3PhaseMemAddr+3,55);
	Write_M8 (profMemAddr.tx3PhaseMemAddr+4,73);
	Write_M8 (profMemAddr.tx3PhaseMemAddr+5,91);
	Write_M8 (profMemAddr.tx3PhaseMemAddr+6,110);

	Write_M8 (profMemAddr.tx4PhaseMemAddr+0,0);
	Write_M8 (profMemAddr.tx4PhaseMemAddr+1,12);
	Write_M8 (profMemAddr.tx4PhaseMemAddr+2,23);
	Write_M8 (profMemAddr.tx4PhaseMemAddr+3,35);
	Write_M8 (profMemAddr.tx4PhaseMemAddr+4,47);
	Write_M8 (profMemAddr.tx4PhaseMemAddr+5,58);
	Write_M8 (profMemAddr.tx4PhaseMemAddr+6,70);
	Write_M8 (profMemAddr.tx4PhaseMemAddr+7,81);
	Write_M8 (profMemAddr.tx4PhaseMemAddr+8,93);
	Write_M8 (profMemAddr.tx4PhaseMemAddr+9,105);
	Write_M8 (profMemAddr.tx4PhaseMemAddr+10,116);


	Write_M8 (profMemAddr.tx5PhaseMemAddr+0,0);
	Write_M8 (profMemAddr.tx5PhaseMemAddr+1,10);
	Write_M8 (profMemAddr.tx5PhaseMemAddr+2,20);
	Write_M8 (profMemAddr.tx5PhaseMemAddr+3,30);
	Write_M8 (profMemAddr.tx5PhaseMemAddr+4,39);
	Write_M8 (profMemAddr.tx5PhaseMemAddr+5,49);
	Write_M8 (profMemAddr.tx5PhaseMemAddr+6,59);
	Write_M8 (profMemAddr.tx5PhaseMemAddr+7,69);
	Write_M8 (profMemAddr.tx5PhaseMemAddr+8,79);
	Write_M8 (profMemAddr.tx5PhaseMemAddr+9,89);
	Write_M8 (profMemAddr.tx5PhaseMemAddr+10,98);
	Write_M8 (profMemAddr.tx5PhaseMemAddr+11,108);
	Write_M8 (profMemAddr.tx5PhaseMemAddr+12,118);

	Write_M8 (profMemAddr.tx6PhaseMemAddr+0,0);
	Write_M8 (profMemAddr.tx6PhaseMemAddr+1,8);
	Write_M8 (profMemAddr.tx6PhaseMemAddr+2,15);
	Write_M8 (profMemAddr.tx6PhaseMemAddr+3,22);
	Write_M8 (profMemAddr.tx6PhaseMemAddr+4,30);
	Write_M8 (profMemAddr.tx6PhaseMemAddr+5,38);
	Write_M8 (profMemAddr.tx6PhaseMemAddr+6,45);
	Write_M8 (profMemAddr.tx6PhaseMemAddr+7,53);
	Write_M8 (profMemAddr.tx6PhaseMemAddr+8,60);
	Write_M8 (profMemAddr.tx6PhaseMemAddr+9,68);
	Write_M8 (profMemAddr.tx6PhaseMemAddr+10,75);
	Write_M8 (profMemAddr.tx6PhaseMemAddr+11,83);
	Write_M8 (profMemAddr.tx6PhaseMemAddr+12,90);
	Write_M8 (profMemAddr.tx6PhaseMemAddr+13,98);
	Write_M8 (profMemAddr.tx6PhaseMemAddr+14,105);
	Write_M8 (profMemAddr.tx6PhaseMemAddr+15,113);
	Write_M8 (profMemAddr.tx6PhaseMemAddr+16,120);

	Write_M8 (profMemAddr.tx7PhaseMemAddr+0,0);
	Write_M8 (profMemAddr.tx7PhaseMemAddr+1,7);
	Write_M8 (profMemAddr.tx7PhaseMemAddr+2,13);
	Write_M8 (profMemAddr.tx7PhaseMemAddr+3,20);
	Write_M8 (profMemAddr.tx7PhaseMemAddr+4,27);
	Write_M8 (profMemAddr.tx7PhaseMemAddr+5,34);
	Write_M8 (profMemAddr.tx7PhaseMemAddr+6,40);
	Write_M8 (profMemAddr.tx7PhaseMemAddr+7,47);
	Write_M8 (profMemAddr.tx7PhaseMemAddr+8,54);
	Write_M8 (profMemAddr.tx7PhaseMemAddr+9,61);
	Write_M8 (profMemAddr.tx7PhaseMemAddr+10,67);
	Write_M8 (profMemAddr.tx7PhaseMemAddr+11,74);
	Write_M8 (profMemAddr.tx7PhaseMemAddr+12,81);
	Write_M8 (profMemAddr.tx7PhaseMemAddr+13,88);
	Write_M8 (profMemAddr.tx7PhaseMemAddr+14,94);
	Write_M8 (profMemAddr.tx7PhaseMemAddr+15,101);
	Write_M8 (profMemAddr.tx7PhaseMemAddr+16,108);
	Write_M8 (profMemAddr.tx7PhaseMemAddr+17,115);
	Write_M8 (profMemAddr.tx7PhaseMemAddr+18,121);

	for(uint32_t i=0;i<64;i++){
		Write_M32 (profMemAddr.testMemAddr+4*i,18012052-6611*i);
	}

	//profile 0: 78G 1000+1000+1000/10+20+20
	profileWave[0].waveCfg0=(0<<12)| //ramp_rma
                            (0<<10)| //A_PLLACC
                            (0<<9)|  //B_PLLACC
                            (0<<8)|  //C_PLLACC
                            (1<<6)|  //A_PAenable
                            (1<<5)|  //B_PAenable
                            (0<<4)|  //C_PAenable
                            (1<<2)|  //ramp_sync_maskA
                            (1<<1)|  //ramp_sync_maskB
                            (1);     //ramp_sync_maskC	
	profileWave[0].lutRampCfg0=(0<<24)|          //rampInterInc[7:0]
							   (1<<16)|          //rampIntraInc[3:0]
							   ((profMemAddr.rampMemAddr-profMemAddr.profileAddr)&0xFFFF);  //rampBaseAddr[15:0]     offset,byte
	profileWave[0].lutRampCfg1=(0<<8)|(2-1);           //rampInterCnt[7:0]  //rampIntraCnt[7:0]
    //profile 1: 78G +0.5M step   10+20+20   2G   idle 9.8304ms
	profileWave[1].waveCfg1=(2<<4)|  //interProfileIdleTimeScaleB
							   (3);     //interProfileIdleTimeValueB
	profileWave[1].lutStartFreqCfg1=((32-1)<<8)|   //startFreqInterCnt[7:0]
									(64-1);    //startFreqIntraCnt[7:0]
	profileWave[1].lutStartFreqCfg2=331*64;       //deltaInterInc_startFreq
  profileWave[1].lutStartFreqCfg3=331;        //deltaIntraInc_startFreq  1=1.5K
//	profileWave[1].lutStartFreqCfg2=0;       //deltaInterInc_startFreq
//  profileWave[1].lutStartFreqCfg3=0;        //deltaIntraInc_startFreq  1=1.5K
    //profile 2:78G 1000+1000+1000/10+20+20
	profileWave[2].waveCfg0=(0<<12)| //ramp_rma
                            (0<<10)| //A_PLLACC
                            (0<<9)|  //B_PLLACC
                            (0<<8)|  //C_PLLACC
                            (1<<6)|  //A_PAenable
                            (1<<5)|  //B_PAenable
                            (0<<4)|  //C_PAenable
                            (1<<2)|  //ramp_sync_maskA
                            (1<<1)|  //ramp_sync_maskB
                            (1);     //ramp_sync_maskC	
	profileWave[2].lutRampCfg0=(0<<24)|          //rampInterInc[7:0]
							   (1<<16)|          //rampIntraInc[3:0]
							   ((profMemAddr.rampMemAddr-profMemAddr.profileAddr)&0xFFFF);  //rampBaseAddr[15:0]     offset,byte
	profileWave[2].lutRampCfg1=(0<<8)|           //rampInterCnt[7:0]
							   (2-1);      //rampIntraCnt[7:0]
    //profile 3: 78G 10+20+20   BPM=2048 idle 13.1072ms
#if 1
	profileWave[3].lutTxEnCfg0=(0<<24)|                //txEnInterInc[7:0]
							   (0<<16)|             //txEnIntraInc[3:0]
							   (((profMemAddr.txEnMemAddr-profMemAddr.profileAddr)+0x10)&0xFFFF);      //txEnBaseAddr[15:0]
	profileWave[3].waveCfg1=(2<<4)|  //interProfileIdleTimeScaleB
							   (4);     //interProfileIdleTimeValueB
	profileWave[3].lutBpmCfg0=(64<<24)|                   //bpmInterInc[7:0]
							  (1<<16)|                    //bpmIntraInc[3:0]
							  ((profMemAddr.bpmMemAddr-profMemAddr.profileAddr)&0xFFFF);    //bpmBaseAddr[15:0]
	profileWave[3].lutBpmCfg1=((32-1)<<8)|                //bpmInterCnt[7:0]
							  (64-1);                     //bpmIntraCnt[7:0]
#endif
    //profile 4:78G 1000+1000+1000/10+20+20
	profileWave[4].waveCfg0=(0<<12)| //ramp_rma
                            (0<<10)| //A_PLLACC
                            (0<<9)|  //B_PLLACC
                            (0<<8)|  //C_PLLACC
                            (1<<6)|  //A_PAenable
                            (1<<5)|  //B_PAenable
                            (0<<4)|  //C_PAenable
                            (1<<2)|  //ramp_sync_maskA
                            (1<<1)|  //ramp_sync_maskB
                            (1);     //ramp_sync_maskC	
	profileWave[4].lutRampCfg0=(0<<24)|          //rampInterInc[7:0]
								  (1<<16)|          //rampIntraInc[3:0]
								  ((profMemAddr.rampMemAddr-profMemAddr.profileAddr)&0xFFFF);  //rampBaseAddr[15:0]     offset,byte
	profileWave[4].lutRampCfg1=(0<<8)|           //rampInterCnt[7:0]
								  (2-1);      //rampIntraCnt[7:0]
    //profile 5: 78G 10+20+20  band=0G   k=60.4K/us  k++  2048pattern idle 16.384ms
#if 1
	profileWave[5].waveCfg1=(2<<4)|  //interProfileIdleTimeScaleB
							   (5);     //interProfileIdleTimeValueB
	profileWave[5].lutRampCfg0=(0<<24)|          //rampInterInc[7:0]
							   (0<<16)|          //rampIntraInc[3:0]
							   (((profMemAddr.rampMemAddr-profMemAddr.profileAddr)+0x30)&0xFFFF);  //rampBaseAddr[15:0]     offset,byte
	profileWave[5].lutRampCfg3=(0<<16)|            //deltaInterInc_ramp_b_time
							   (64);              //deltaInterInc_ramp_b_inc
	profileWave[5].lutRampCfg6=(0<<16)|            //deltaIntraInc_ramp_b_time
								  (1);            //deltaIntraInc_ramp_b_inc
#endif
    //profile 6:78G 1000+1000+1000/10+20+20
	profileWave[6].waveCfg0=(0<<12)| //ramp_rma
                            (0<<10)| //A_PLLACC
                            (0<<9)|  //B_PLLACC
                            (0<<8)|  //C_PLLACC
                            (1<<6)|  //A_PAenable
                            (1<<5)|  //B_PAenable
                            (0<<4)|  //C_PAenable
                            (1<<2)|  //ramp_sync_maskA
                            (1<<1)|  //ramp_sync_maskB
                            (1);     //ramp_sync_maskC	
	profileWave[6].lutRampCfg0=(0<<24)|          //rampInterInc[7:0]
								  (1<<16)|          //rampIntraInc[3:0]
								  ((profMemAddr.rampMemAddr-profMemAddr.profileAddr)&0xFFFF);  //rampBaseAddr[15:0]     offset,byte
	profileWave[6].lutRampCfg1=(0<<8)|           //rampInterCnt[7:0]
								  (2-1);         //rampIntraCnt[7:0]
    //profile 7:78G 10+20+20 tx0-6 txPhase:0,1/8...7/8 idle 19.6608ms
#if 1
	profileWave[7].waveCfg1=(2<<4)|  //interProfileIdleTimeScaleB
							   (6);     //interProfileIdleTimeValueB
	profileWave[7].lutTxEnCfg0=(0<<24)|                  //txEnInterInc[7:0]
							   (0<<16)|                  //txEnIntraInc[3:0]
							   (((profMemAddr.txEnMemAddr-profMemAddr.profileAddr)+0x30+0)&0xFFFF); //txEnBaseAddr[15:0]
	profileWave[7].lutTx0PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx0PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[7].lutTx0PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(3-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[7].lutTx1PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx1PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[7].lutTx1PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(4-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[7].lutTx2PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx2PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[7].lutTx2PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(5-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[7].lutTx3PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx3PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[7].lutTx3PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(7-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[7].lutTx4PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx4PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[7].lutTx4PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(11-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[7].lutTx5PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx5PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[7].lutTx5PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(13-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[7].lutTx6PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx6PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[7].lutTx6PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(17-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
#endif
    //profile 8:78G 1000+1000+1000/10+20+20
	profileWave[8].waveCfg0=(0<<12)| //ramp_rma
                            (0<<10)| //A_PLLACC
                            (0<<9)|  //B_PLLACC
                            (0<<8)|  //C_PLLACC
                            (1<<6)|  //A_PAenable
                            (1<<5)|  //B_PAenable
                            (0<<4)|  //C_PAenable
                            (1<<2)|  //ramp_sync_maskA
                            (1<<1)|  //ramp_sync_maskB
                            (1);     //ramp_sync_maskC	
	profileWave[8].lutRampCfg0=(0<<24)|          //rampInterInc[7:0]
							   (1<<16)|          //rampIntraInc[3:0]
							   ((profMemAddr.rampMemAddr-profMemAddr.profileAddr)&0xFFFF);  //rampBaseAddr[15:0]     offset,byte
	profileWave[8].lutRampCfg1=(0<<8)|           //rampInterCnt[7:0]
							   (2-1);      //rampIntraCnt[7:0]
    //profile 9:78G 10+20+20 1G txEn 0-7 ++
	profileWave[9].anaCfg0=rc8088_regCfg->ANA.CFG01.WORD;//vcoband 1
	profileWave[9].lutRampCfg0=(0<<24)|          //rampInterInc[7:0]
								  (0<<16)|          //rampIntraInc[3:0]
								  (((profMemAddr.rampMemAddr-profMemAddr.profileAddr)+0x40)&0xFFFF);  //rampBaseAddr[15:0]     offset,byte
	profileWave[9].waveCfg1=(2<<4)|  //interProfileIdleTimeScaleB
							   (7);     //interProfileIdleTimeValueB
	profileWave[9].lutTxEnCfg0=(0<<24)|                //txEnInterInc[7:0]
							   (1<<16)|             //txEnIntraInc[3:0]
							   (((profMemAddr.txEnMemAddr-profMemAddr.profileAddr)+0x20)&0xFFFF);      //txEnBaseAddr[15:0]
	profileWave[9].lutTxEnCfg1=(0<<8)|                 //txEnInterCnt[7:0]
							   (8-1);                    //txEnIntraCnt[7:0]
    //profile 10:78G 1000+1000+1000/10+20+20
	profileWave[10].waveCfg0=(0<<12)| //ramp_rma
                            (0<<10)| //A_PLLACC
                            (0<<9)|  //B_PLLACC
                            (0<<8)|  //C_PLLACC
                            (1<<6)|  //A_PAenable
                            (1<<5)|  //B_PAenable
                            (0<<4)|  //C_PAenable
                            (1<<2)|  //ramp_sync_maskA
                            (1<<1)|  //ramp_sync_maskB
                            (1);     //ramp_sync_maskC	 
	profileWave[10].lutRampCfg0=(0<<24)|          //rampInterInc[7:0]
							    (1<<16)|          //rampIntraInc[3:0]
								((profMemAddr.rampMemAddr-profMemAddr.profileAddr)&0xFFFF);  //rampBaseAddr[15:0]     offset,byte
	profileWave[10].lutRampCfg1=(0<<8)|           //rampInterCnt[7:0]
								  (2-1);      //rampIntraCnt[7:0]
    //profile 11:78G 10+20+20 2G step 0.5M++ tx0-6 txPhase 0/8-7/8
	profileWave[11].waveCfg1=(2<<4)|  //interProfileIdleTimeScaleB
							   (8);     //interProfileIdleTimeValueB
	profileWave[11].lutStartFreqCfg1=((32-1)<<8)|   //startFreqInterCnt[7:0]
									(64-1);    //startFreqIntraCnt[7:0]
	profileWave[11].lutStartFreqCfg2=331*64;       //deltaInterInc_startFreq
    profileWave[11].lutStartFreqCfg3=331;        //deltaIntraInc_startFreq  1=1.5K
	profileWave[11].lutTxEnCfg0=(0<<24)|                //txEnInterInc[7:0]
							   (0<<16)|             //txEnIntraInc[3:0]
							   (((profMemAddr.txEnMemAddr-profMemAddr.profileAddr)+0x30)&0xFFFF);      //txEnBaseAddr[15:0]
	profileWave[11].lutTx0PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx0PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[11].lutTx0PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(3-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[11].lutTx1PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx1PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[11].lutTx1PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(4-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[11].lutTx2PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx2PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[11].lutTx2PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(5-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[11].lutTx3PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx3PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[11].lutTx3PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(7-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[11].lutTx4PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx4PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[11].lutTx4PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(11-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[11].lutTx5PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx5PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[11].lutTx5PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(13-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[11].lutTx6PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx6PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[11].lutTx6PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(17-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
    //profile 12:78G 1000+1000+1000/10+20+20
	profileWave[12].waveCfg0=(0<<12)| //ramp_rma
                            (0<<10)| //A_PLLACC
                            (0<<9)|  //B_PLLACC
                            (0<<8)|  //C_PLLACC
                            (1<<6)|  //A_PAenable
                            (1<<5)|  //B_PAenable
                            (0<<4)|  //C_PAenable
                            (1<<2)|  //ramp_sync_maskA
                            (1<<1)|  //ramp_sync_maskB
                            (1);     //ramp_sync_maskC	
	profileWave[12].lutRampCfg0=(0<<24)|          //rampInterInc[7:0]
								  (1<<16)|          //rampIntraInc[3:0]
								  ((profMemAddr.rampMemAddr-profMemAddr.profileAddr)&0xFFFF);  //rampBaseAddr[15:0]     offset,byte
	profileWave[12].lutRampCfg1=(0<<8)|           //rampInterCnt[7:0]
								  (2-1);      //rampIntraCnt[7:0]
    //profile 13:78G 10+20+20 2G tx0-6 bpm 2048 pattern  txPhase 0/8-7/8
	profileWave[13].waveCfg1=(2<<4)|  //interProfileIdleTimeScaleB
							   (9);     //interProfileIdleTimeValueB
	profileWave[13].lutTxEnCfg0=(0<<24)|                //txEnInterInc[7:0]
							   (0<<16)|             //txEnIntraInc[3:0]
							   (((profMemAddr.txEnMemAddr-profMemAddr.profileAddr)+0x30)&0xFFFF);      //txEnBaseAddr[15:0]
	profileWave[13].lutBpmCfg0=(64<<24)|                   //bpmInterInc[7:0]
							  (1<<16)|                    //bpmIntraInc[3:0]
							  ((profMemAddr.bpmMemAddr-profMemAddr.profileAddr)&0xFFFF);    //bpmBaseAddr[15:0]
	profileWave[13].lutBpmCfg1=((32-1)<<8)|                //bpmInterCnt[7:0]
							  (64-1);                     //bpmIntraCnt[7:0]
	profileWave[13].lutTx0PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx0PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[13].lutTx0PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(3-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[13].lutTx1PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx1PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[13].lutTx1PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(4-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[13].lutTx2PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx2PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[13].lutTx2PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(5-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[13].lutTx3PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx3PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[13].lutTx3PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(7-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[13].lutTx4PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx4PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[13].lutTx4PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(11-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[13].lutTx5PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx5PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[13].lutTx5PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(13-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[13].lutTx6PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx6PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[13].lutTx6PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(17-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
    //profile 14:78G 1000+1000+1000/10+20+20
	profileWave[14].waveCfg0=(0<<12)| //ramp_rma
                            (0<<10)| //A_PLLACC
                            (0<<9)|  //B_PLLACC
                            (0<<8)|  //C_PLLACC
                            (1<<6)|  //A_PAenable
                            (1<<5)|  //B_PAenable
                            (0<<4)|  //C_PAenable
                            (1<<2)|  //ramp_sync_maskA
                            (1<<1)|  //ramp_sync_maskB
                            (1);     //ramp_sync_maskC	
	profileWave[14].lutRampCfg0=(0<<24)|          //rampInterInc[7:0]
								  (1<<16)|          //rampIntraInc[3:0]
								  ((profMemAddr.rampMemAddr-profMemAddr.profileAddr)&0xFFFF);  //rampBaseAddr[15:0]     offset,byte
	profileWave[14].lutRampCfg1=(0<<8)|           //rampInterCnt[7:0]
								  (2-1);      //rampIntraCnt[7:0]
    //profile 15:78G 10+20+20 2G stepK 1M/us  stepT 0.1us  32pattern  adcRma 2pattern
	profileWave[15].waveCfg1=(2<<4)|  //interProfileIdleTimeScaleB
							   (10);     //interProfileIdleTimeValueB
	profileWave[15].lutRampCfg3=((4)<<16)|          //deltaInterInc_ramp_b_time
								  (0);              //deltaInterInc_ramp_b_inc
	profileWave[15].lutRampCfg6=(0<<16)|          //deltaIntraInc_ramp_b_time
								  (16);              //deltaIntraInc_ramp_b_inc
	profileWave[15].lutAdcRmaCfg0=(1<<24)|              //adcRmaInterInc[7:0]
									(0<<16)|              //adcRmaIntraInc[3:0]
									((profMemAddr.adcRmaMemAddr-profMemAddr.profileAddr)&0xFFFF);    //adcRmaBaseAddr[15:0]
	profileWave[15].lutAdcRmaCfg1=((8-1)<<8)|               //adcRmaInterCnt[7:0]
									(256-1);                  //adcRmaIntraCnt[7:0]
    //profile 16:78G 1000+1000+1000/10+20+20
	profileWave[16].waveCfg0=(0<<12)| //ramp_rma
                            (0<<10)| //A_PLLACC
                            (0<<9)|  //B_PLLACC
                            (0<<8)|  //C_PLLACC
                            (1<<6)|  //A_PAenable
                            (1<<5)|  //B_PAenable
                            (0<<4)|  //C_PAenable
                            (1<<2)|  //ramp_sync_maskA
                            (1<<1)|  //ramp_sync_maskB
                            (1);     //ramp_sync_maskC	
	profileWave[16].lutRampCfg0=(0<<24)|          //rampInterInc[7:0]
								  (1<<16)|          //rampIntraInc[3:0]
								  ((profMemAddr.rampMemAddr-profMemAddr.profileAddr)&0xFFFF);  //rampBaseAddr[15:0]     offset,byte
	profileWave[16].lutRampCfg1=(0<<8)|           //rampInterCnt[7:0]
								  (2-1);      //rampIntraCnt[7:0]
    //profile 17:78G 10+20+20 2G tx0-4 bpm 640pattern  anaCfg RX Gain
	profileWave[17].lutRampCfg1=((10-1)<<8)|           //rampInterCnt[7:0]
								  (64-1);      //rampIntraCnt[7:0]
	profileWave[17].lutTxEnCfg0=(0<<24)|                //txEnInterInc[7:0]
							   (1<<16)|             //txEnIntraInc[3:0]
							   (((profMemAddr.txEnMemAddr-profMemAddr.profileAddr)+0)&0xFFFF);      //txEnBaseAddr[15:0]
	profileWave[17].lutTxEnCfg1=(0<<8)|                 //txEnInterCnt[7:0]
							   (5-1);                    //txEnIntraCnt[7:0]
	profileWave[17].lutBpmCfg0=(1<<24)|                   //bpmInterInc[7:0]
							  (0<<16)|                    //bpmIntraInc[3:0]
							  ((profMemAddr.bpmMemAddr-profMemAddr.profileAddr)&0xFFFF);    //bpmBaseAddr[15:0]
	profileWave[17].lutBpmCfg1=((128-1)<<8)|                //bpmInterCnt[7:0]
							  (5-1);                     //bpmIntraCnt[7:0]
	profileWave[17].anaCfg4=0x00004FBA;
    //profile 18:78G 10+20+20 2G tx0-4 bpm 640pattern  anaCfg RX Gain
	profileWave[18].lutRampCfg1=((10-1)<<8)|           //rampInterCnt[7:0]
								  (64-1);      //rampIntraCnt[7:0]
	profileWave[18].lutTxEnCfg0=(0<<24)|                //txEnInterInc[7:0]
							   (1<<16)|             //txEnIntraInc[3:0]
							   (((profMemAddr.txEnMemAddr-profMemAddr.profileAddr)+0)&0xFFFF);      //txEnBaseAddr[15:0]
	profileWave[18].lutTxEnCfg1=(0<<8)|                 //txEnInterCnt[7:0]
							   (5-1);                    //txEnIntraCnt[7:0]
	profileWave[18].lutBpmCfg0=(1<<24)|                   //bpmInterInc[7:0]
							  (0<<16)|                    //bpmIntraInc[3:0]
							  (((profMemAddr.bpmMemAddr-profMemAddr.profileAddr)+128)&0xFFFF);    //bpmBaseAddr[15:0]
	profileWave[18].lutBpmCfg1=((128-1)<<8)|                //bpmInterCnt[7:0]
							  (5-1);                     //bpmIntraCnt[7:0]
	profileWave[18].anaCfg4=0x00004FB5;
    //profile 19:78G 10+20+20 2G tx5-7 bpm 768pattern  anaCfg Power
	profileWave[19].waveCfg1=(2<<4)|  //interProfileIdleTimeScaleB
							   (11);     //interProfileIdleTimeValueB
	profileWave[19].lutRampCfg1=((12-1)<<8)|           //rampInterCnt[7:0]
								  (64-1);      //rampIntraCnt[7:0]
	profileWave[19].lutTxEnCfg0=(0<<24)|                //txEnInterInc[7:0]
							   (1<<16)|             //txEnIntraInc[3:0]
							   (((profMemAddr.txEnMemAddr-profMemAddr.profileAddr)+0x10)&0xFFFF);      //txEnBaseAddr[15:0]
	profileWave[19].lutTxEnCfg1=(0<<8)|                 //txEnInterCnt[7:0]
							   (3-1);                    //txEnIntraCnt[7:0]
	profileWave[19].lutBpmCfg0=(1<<24)|                   //bpmInterInc[7:0]
							  (0<<16)|                    //bpmIntraInc[3:0]
							  (((profMemAddr.bpmMemAddr-profMemAddr.profileAddr)+256)&0xFFFF);    //bpmBaseAddr[15:0]
	profileWave[19].lutBpmCfg1=((256-1)<<8)|                //bpmInterCnt[7:0]
							  (3-1);                     //bpmIntraCnt[7:0]
//	profileWave[19].powerCfg1 = 0; //idle:0
    //profile 20:78G 1000+1000+1000/10+20+20
	profileWave[20].waveCfg0=(0<<12)| //ramp_rma
                            (0<<10)| //A_PLLACC
                            (0<<9)|  //B_PLLACC
                            (0<<8)|  //C_PLLACC
                            (1<<6)|  //A_PAenable
                            (1<<5)|  //B_PAenable
                            (0<<4)|  //C_PAenable
                            (1<<2)|  //ramp_sync_maskA
                            (1<<1)|  //ramp_sync_maskB
                            (1);     //ramp_sync_maskC	
	profileWave[20].lutRampCfg0=(0<<24)|          //rampInterInc[7:0]
								  (1<<16)|          //rampIntraInc[3:0]
								  ((profMemAddr.rampMemAddr-profMemAddr.profileAddr)&0xFFFF);  //rampBaseAddr[15:0]     offset,byte
	profileWave[20].lutRampCfg1=(0<<8)|           //rampInterCnt[7:0]
								  (2-1);      //rampIntraCnt[7:0]
    //profile 21:78G 10+20+20 2G tx0-6 bpm 768pattern  txPhase 0-6/8 anaCfg RX Gain
	profileWave[21].lutRampCfg1=((12-1)<<8)|           //rampInterCnt[7:0]
								  (64-1);      //rampIntraCnt[7:0]
	profileWave[21].lutTxEnCfg0=(0<<24)|                //txEnInterInc[7:0]
							   (0<<16)|             //txEnIntraInc[3:0]
							   (((profMemAddr.txEnMemAddr-profMemAddr.profileAddr)+0x30)&0xFFFF);      //txEnBaseAddr[15:0]
	profileWave[21].lutTxEnCfg1=(0<<8)|                 //txEnInterCnt[7:0]
							   (1-1);                    //txEnIntraCnt[7:0]
	profileWave[21].lutBpmCfg0=(64<<24)|                   //bpmInterInc[7:0]
							   (1<<16)|                    //bpmIntraInc[3:0]
							   ((profMemAddr.bpmMemAddr-profMemAddr.profileAddr)&0xFFFF);    //bpmBaseAddr[15:0]
	profileWave[21].lutBpmCfg1=((12-1)<<8)|                //bpmInterCnt[7:0]
							  (64-1);                     //bpmIntraCnt[7:0]
	profileWave[21].lutTx0PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx0PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[21].lutTx0PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(3-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[21].lutTx1PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx1PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[21].lutTx1PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(4-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[21].lutTx2PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx2PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[21].lutTx2PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(5-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[21].lutTx3PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx3PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[21].lutTx3PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(7-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[21].lutTx4PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx4PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[21].lutTx4PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(11-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[21].lutTx5PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx5PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[21].lutTx5PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(13-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[21].lutTx6PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx6PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[21].lutTx6PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(17-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[21].anaCfg4=0x00004FBA;
    //profile 22:78G 10+20+20 2G tx1-7 bpm 512pattern  txPhase 0-6/8 anaCfg RX Gain
	profileWave[22].lutRampCfg1=((8-1)<<8)|           //rampInterCnt[7:0]
								  (64-1);      //rampIntraCnt[7:0]
	profileWave[22].lutTxEnCfg0=(0<<24)|                //txEnInterInc[7:0]
							   (0<<16)|             //txEnIntraInc[3:0]
							   (((profMemAddr.txEnMemAddr-profMemAddr.profileAddr)+0x40)&0xFFFF);      //txEnBaseAddr[15:0]
	profileWave[22].lutTxEnCfg1=(0<<8)|                 //txEnInterCnt[7:0]
							   (1-1);                    //txEnIntraCnt[7:0]
	profileWave[22].lutBpmCfg0=(64<<24)|                   //bpmInterInc[7:0]
							   (1<<16)|                    //bpmIntraInc[3:0]
							   (((profMemAddr.bpmMemAddr-profMemAddr.profileAddr)+768)&0xFFFF);    //bpmBaseAddr[15:0]
	profileWave[22].lutBpmCfg1=((8-1)<<8)|                //bpmInterCnt[7:0]
							  (64-1);                     //bpmIntraCnt[7:0]
	profileWave[22].lutTx1PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx1PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[22].lutTx1PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(4-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[22].lutTx2PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx2PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[22].lutTx2PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(5-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[22].lutTx3PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx3PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[22].lutTx3PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(7-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[22].lutTx4PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx4PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[22].lutTx4PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(11-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[22].lutTx5PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx5PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[22].lutTx5PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(13-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[22].lutTx6PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx6PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[22].lutTx6PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(17-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[22].lutTx7PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx7PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[22].lutTx7PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(19-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[22].anaCfg4=0x00004FB5;
    //profile 23:78G 10+20+20 2G tx0-3 bpm 768pattern  txPhase 0-3/6 anaCfg Power
	profileWave[23].waveCfg1=(2<<4)|  //interProfileIdleTimeScaleB
							   (12);     //interProfileIdleTimeValueB
	profileWave[23].lutRampCfg1=((12-1)<<8)|           //rampInterCnt[7:0]
								  (64-1);      //rampIntraCnt[7:0]
	profileWave[23].lutTxEnCfg0=(0<<24)|                //txEnInterInc[7:0]
							   (0<<16)|             //txEnIntraInc[3:0]
							   (((profMemAddr.txEnMemAddr-profMemAddr.profileAddr)+0x50)&0xFFFF);      //txEnBaseAddr[15:0]
	profileWave[23].lutTxEnCfg1=(0<<8)|                 //txEnInterCnt[7:0]
							   (1-1);                    //txEnIntraCnt[7:0]
	profileWave[23].lutBpmCfg0=(64<<24)|                   //bpmInterInc[7:0]
							   (1<<16)|                    //bpmIntraInc[3:0]
							   (((profMemAddr.bpmMemAddr-profMemAddr.profileAddr)+1280)&0xFFFF);    //bpmBaseAddr[15:0]
	profileWave[23].lutBpmCfg1=((12-1)<<8)|                //bpmInterCnt[7:0]
							  (64-1);                     //bpmIntraCnt[7:0]

	profileWave[23].lutTx0PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx0PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[23].lutTx0PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(3-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[23].lutTx1PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx1PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[23].lutTx1PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(4-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[23].lutTx2PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx2PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[23].lutTx2PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(5-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[23].lutTx3PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx3PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[23].lutTx3PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(7-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt


//	profileWave[23].powerCfg1 = 0; //idle:0
    //profile 24:78G 1000+1000+1000/10+20+20
	profileWave[24].waveCfg0=(0<<12)| //ramp_rma
                            (0<<10)| //A_PLLACC
                            (0<<9)|  //B_PLLACC
                            (0<<8)|  //C_PLLACC
                            (1<<6)|  //A_PAenable
                            (1<<5)|  //B_PAenable
                            (0<<4)|  //C_PAenable
                            (1<<2)|  //ramp_sync_maskA
                            (1<<1)|  //ramp_sync_maskB
                            (1);     //ramp_sync_maskC	
	profileWave[24].lutRampCfg0=(0<<24)|          //rampInterInc[7:0]
								  (1<<16)|          //rampIntraInc[3:0]
								  ((profMemAddr.rampMemAddr-profMemAddr.profileAddr)&0xFFFF);  //rampBaseAddr[15:0]     offset,byte
	profileWave[24].lutRampCfg1=(0<<8)|           //rampInterCnt[7:0]
								  (2-1);      //rampIntraCnt[7:0]

    //profile 25:78G 10+20+20 2G step 1.2337M++ tx0-6 bpm 768pattern  txPhase 0-6/8 anaCfg RX Gain
	profileWave[25].lutRampCfg1=((12-1)<<8)|           //rampInterCnt[7:0]
								  (64-1);      //rampIntraCnt[7:0]
	profileWave[25].lutStartFreqCfg1=((12-1)<<8)|   //startFreqInterCnt[7:0]
									(64-1);    //startFreqIntraCnt[7:0]
	profileWave[25].lutStartFreqCfg2=817*64;       //deltaInterInc_startFreq
    profileWave[25].lutStartFreqCfg3=817;        //deltaIntraInc_startFreq  1=1.51K
	profileWave[25].lutTxEnCfg0=(0<<24)|                //txEnInterInc[7:0]
							   (0<<16)|             //txEnIntraInc[3:0]
							   (((profMemAddr.txEnMemAddr-profMemAddr.profileAddr)+0x30)&0xFFFF);      //txEnBaseAddr[15:0]
	profileWave[25].lutTxEnCfg1=(0<<8)|                 //txEnInterCnt[7:0]
							   (1-1);                    //txEnIntraCnt[7:0]
	profileWave[25].lutBpmCfg0=(64<<24)|                   //bpmInterInc[7:0]
							   (1<<16)|                    //bpmIntraInc[3:0]
							   ((profMemAddr.bpmMemAddr-profMemAddr.profileAddr)&0xFFFF);    //bpmBaseAddr[15:0]
	profileWave[25].lutBpmCfg1=((12-1)<<8)|                //bpmInterCnt[7:0]
							  (64-1);                     //bpmIntraCnt[7:0]
	profileWave[25].lutTx0PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx0PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[25].lutTx0PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(3-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[25].lutTx1PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx1PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[25].lutTx1PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(4-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[25].lutTx2PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx2PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[25].lutTx2PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(5-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[25].lutTx3PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx3PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[25].lutTx3PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(7-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[25].lutTx4PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx4PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[25].lutTx4PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(11-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[25].lutTx5PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx5PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[25].lutTx5PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(13-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[25].lutTx6PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx6PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[25].lutTx6PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(17-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[25].anaCfg4=0x00004FBA;
	//profile 26:78G 10+20+20 2G step 1.8506M++ tx1-7 bpm 512pattern  txPhase 0-6/8 anaCfg RX Gain
	profileWave[26].lutRampCfg1=((8-1)<<8)|           //rampInterCnt[7:0]
								  (64-1);      //rampIntraCnt[7:0]
//	profileWave[26].lutRampCfg3=(0<<16)|          //deltaInterInc_ramp_b_time
//								  (0);              //deltaInterInc_ramp_b_inc
//	profileWave[26].lutRampCfg6=((-2000)<<16)|          //deltaIntraInc_ramp_b_time
//								  (0);              //deltaIntraInc_ramp_b_inc
	profileWave[26].lutStartFreqCfg1=((8-1)<<8)|   //startFreqInterCnt[7:0]
									(64-1);    //startFreqIntraCnt[7:0]
	profileWave[26].lutStartFreqCfg2=1226*64;       //deltaInterInc_startFreq
    profileWave[26].lutStartFreqCfg3=1226;        //deltaIntraInc_startFreq  1=1.51K
	profileWave[26].lutTxEnCfg0=(0<<24)|                //txEnInterInc[7:0]
							   (0<<16)|             //txEnIntraInc[3:0]
							   (((profMemAddr.txEnMemAddr-profMemAddr.profileAddr)+0x40)&0xFFFF);      //txEnBaseAddr[15:0]
	profileWave[26].lutTxEnCfg1=(0<<8)|                 //txEnInterCnt[7:0]
							   (1-1);                    //txEnIntraCnt[7:0]
	profileWave[26].lutBpmCfg0=(64<<24)|                   //bpmInterInc[7:0]
							   (1<<16)|                    //bpmIntraInc[3:0]
							   (((profMemAddr.bpmMemAddr-profMemAddr.profileAddr)+768)&0xFFFF);    //bpmBaseAddr[15:0]
	profileWave[26].lutBpmCfg1=((8-1)<<8)|                //bpmInterCnt[7:0]
							  (64-1);                     //bpmIntraCnt[7:0]
	profileWave[26].lutTx1PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx1PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[26].lutTx1PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(4-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[26].lutTx2PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx2PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[26].lutTx2PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(5-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[26].lutTx3PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx3PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[26].lutTx3PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(7-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[26].lutTx4PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx4PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[26].lutTx4PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(11-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[26].lutTx5PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx5PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[26].lutTx5PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(13-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[26].lutTx6PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx6PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[26].lutTx6PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(17-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[26].lutTx7PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx7PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[26].lutTx7PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(19-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[26].anaCfg4=0x00004FB5;
	//profile 27:78G 10+20+20 2G step 0.5M++ tx0-3 bpm 768pattern  txPhase 0-3/6 anaCfg Power
	profileWave[27].waveCfg1=(2<<4)|  //interProfileIdleTimeScaleB
							   (13);     //interProfileIdleTimeValueB
	profileWave[27].lutRampCfg1=((12-1)<<8)|           //rampInterCnt[7:0]
								  (64-1);      //rampIntraCnt[7:0]
	profileWave[27].lutStartFreqCfg1=((12-1)<<8)|   //startFreqInterCnt[7:0]
									(64-1);    //startFreqIntraCnt[7:0]
	profileWave[27].lutStartFreqCfg2=817*64;       //deltaInterInc_startFreq
    profileWave[27].lutStartFreqCfg3=817;        //deltaIntraInc_startFreq  1=1.51K
	profileWave[27].lutRampCfg1=((12-1)<<8)|           //rampInterCnt[7:0]
								  (64-1);      //rampIntraCnt[7:0]
	profileWave[27].lutTxEnCfg0=(0<<24)|                //txEnInterInc[7:0]
							   (0<<16)|             //txEnIntraInc[3:0]
							   (((profMemAddr.txEnMemAddr-profMemAddr.profileAddr)+0x50)&0xFFFF);      //txEnBaseAddr[15:0]
	profileWave[27].lutTxEnCfg1=(0<<8)|                 //txEnInterCnt[7:0]
							   (1-1);                    //txEnIntraCnt[7:0]
	profileWave[27].lutBpmCfg0=(64<<24)|                   //bpmInterInc[7:0]
							   (1<<16)|                    //bpmIntraInc[3:0]
							   (((profMemAddr.bpmMemAddr-profMemAddr.profileAddr)+1280)&0xFFFF);    //bpmBaseAddr[15:0]
	profileWave[27].lutBpmCfg1=((12-1)<<8)|                //bpmInterCnt[7:0]
							  (64-1);                     //bpmIntraCnt[7:0]
	profileWave[27].lutTx0PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx0PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[27].lutTx0PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(3-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[27].lutTx1PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx1PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[27].lutTx1PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(4-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[27].lutTx2PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx2PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[27].lutTx2PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(5-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
	profileWave[27].lutTx3PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx3PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
	profileWave[27].lutTx3PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(7-1);                //deltaInterInc,deltaIntraInc,interCnt,intraCnt
//	profileWave[27].powerCfg1 = 0; //idle:0



	HAL_RC8088_WrMem(&RC8088_RW, RC8088_CBUFF_BASE,rc8088_userCfg->userMemAddr.cBuf_Addr, 8192>>4);
	HAL_RC8088_RdMem(&RC8088_RW, RC8088_CBUFF_BASE, (RC8088_MemDat_st *)TEST_READ_MEM_ADDR, (8192)>>4);
}
#endif 

#if TEST_TXPHASE_WAVE_EN
/*
	QT generate need to config list :
	prep:numPT=1024
	numRX:4
	profileMan:numChirp=128
	startFreq=78G
	bandwidth=1G
	MIPI: laneSpeed=800M
	
	QT sample need to config list:
	numFrame=128
	numChirp=128
	numPT=1024
	numByte=2
	numRX=1
	
*/
const uint16_t txpBuf_Idx0_127[]={ //tx1-tx8
//�Ƿ�
//64162,64156,65172,65166,64648,64642,64636,65140,64112,64616,63588,63582,62552,62034,62028,61510,59970,59964,58934,57396,56878,55848,54310,53792,52254,50714,49686,48148,47120,45582,44042,42504,40968,39430,37384,35846,34308,32774,31238,29188,27654,26118,24586,23052,21004,19470,18452,16918,15386,14366,12320,11300,10796,8750,8244,7226,6208,5188,4170,3664,3158,2652,2658,2152,1134,2164,1146,1664,1670,1676,1170,1688,2206,2212,3240,3758,3764,4792,5820,5826,6854,7882,8910,8916,10454,11994,12510,13028,14564,15594,16620,17646,18674,20210,21746,22774,24312,25848,27386,28412,29950,31486,33020,34558,36092,37630,39164,40698,42234,43768,45302,46322,47854,49388,50408,51428,52960,53980,55512,57044,58064,58570,59588,61120,61626,62644,62638,63656
//ģ����
62034,62028,60482,59968,59450,56882,57390,56364,55338,53798,52252,50716,50202,49174,48148,46096,44560,41992,40458,38920,37892,36356,34820,32772,31750,29700,28678,26632,24584,24072,22542,21518,19982,18450,16918,15388,13852,12836,11812,10794,9774,8240,6712,6206,5186,4684,3662,3156,3164,2146,1642,1648,1142,1146,1156,1672,1678,1682,1690,2718,2214,3754,4272,3766,5306,6336,6852,7368,7884,8400,10452,10966,11996,13024,15080,16104,16618,17134,18158,19184,20722,22262,22776,24312,24826,25850,29948,31484,31486,32510,34558,36094,38652,37626,38650,40698,43766,44788,45812,46832,48878,49900,52454,53474,53982,55516,57556,57040,58570,60100,60610,61114,62134,63152,63656,64164,64670,64154,64660,65164,64646,64636,64116,64622,64106,64098,64092,62550
};

void RC8088_ProfileLutTXPhaseConfig(void){
	STRUCT_PROFILELUT *profileWave=(STRUCT_PROFILELUT *)profMemAddr.profileAddr;
    memset((uint8_t *)TEST_WRITE_MEM_ADDR,0,16*128);
    HAL_RC8088_WrMem(&RC8088_RW, RC8088_TXBUFF_BASE, (RC8088_MemDat_st *)TEST_WRITE_MEM_ADDR, (16*128)>>4);//len:1=16Byte
    HAL_RC8088_RdMem(&RC8088_RW, RC8088_TXBUFF_BASE, (RC8088_MemDat_st *)TEST_READ_MEM_ADDR, (16*128)>>4);
	//write cbuf
	#if 0 //txI++
		for(uint32_t i=0;i<128;i++){
			for(uint32_t j=0;j<8;j++){
				txpBuf[i][j].txI=i<<1;
				txpBuf[i][j].txQ=0;
			}
		}
		RF_WriteMemSPI_128B(RC8088_MEM_TXPBUF,(uint8_t *)&txpBuf[0][0],2048>>4);
		RF_ReadMemSPI_128B(RC8088_MEM_TXPBUF,(uint8_t *)BB_ABUF1_BASE,2048>>4);
	#endif
	#if 1 //const
		for (uint32_t j=0;j<128;j++){
			for(uint32_t i=0;i<8;i++){
//                Write_M16(TEST_WRITE_MEM_ADDR+i*2+j*16,txpBuf_Idx0_127[j]);
				Write_M16(TEST_WRITE_MEM_ADDR+i*2+j*16,txpBuf_Idx0_127[j+i*128]);
			}
		}
		HAL_RC8088_WrMem(&RC8088_RW, RC8088_TXBUFF_BASE, (RC8088_MemDat_st *)TEST_WRITE_MEM_ADDR, (16*128)>>4);//len:1=16Byte
		HAL_RC8088_RdMem(&RC8088_RW, RC8088_TXBUFF_BASE, (RC8088_MemDat_st *)TEST_READ_MEM_ADDR, (16*128)>>4);
	#endif
	//config init
    #if TEST_TXPHASE_SHOW_EN
        rc8088_userCfg->numFrame=1;//numTX=8->128*8
    #else
        rc8088_userCfg->numFrame=1280;//numTX=8->128*8
    #endif
//	rc8088_userCfg->numProf = 1;
//	rc8088_userCfg->adcRmaInitVal=250;
	rc8088_regCfg->PROFILE_MAN.ProfileMan_CFG0.BIT.profile_man_vld=0;
	HAL_RC8088_WrReg(&RC8088_RW, &rc8088_regCfg->PROFILE_MAN.ProfileMan_CFG0, 1);
	//subframe
	rc8088_regCfg->SF.SF_CFG0.BIT.sf0_profileLoopInf          =0;
	rc8088_regCfg->SF.SF_CFG0.BIT.sf0_profileLoopNum          =1-1;
	rc8088_regCfg->SF.SF_CFG0.BIT.sf0_profileNumA             =0;
	rc8088_regCfg->SF.SF_CFG0.BIT.sf0_profileNumB             =0;
	rc8088_regCfg->SF.SF_CFG0.BIT.sf0_interFrameIdleTimeScaleB=0;
	rc8088_regCfg->SF.SF_CFG0.BIT.sf0_interFrameIdleTimeValueB=0;
	HAL_RC8088_WrReg(&RC8088_RW, &rc8088_regCfg->SF.SF_CFG0, 1);
	//write profile addr
    #if TEST_TXPHASE_SHOW_EN
    #else
        uint32_t deltaIntraInc_tx0Phase=1;//0,1,16,32,48
    #endif
	
  for (uint32_t sCnt=0;sCnt<1;sCnt++){
		profileWave[sCnt].waveCfg0=(0<<12)| //ramp_rma
															 (0<<10)| //A_PLLACC
															 (0<<9)|  //B_PLLACC
															 (0<<8)|  //C_PLLACC
															 (1<<6)|  //A_PAenable
															 (1<<5)|  //B_PAenable
															 (0<<4)|  //C_PAenable
															 (1<<2)|  //ramp_sync_maskA
															 (0<<1)|  //ramp_sync_maskB
															 (0);     //ramp_sync_maskC
		profileWave[sCnt].waveCfg1=(0<<4)|  //interProfileIdleTimeScaleB
															 (0);     //interProfileIdleTimeValueB
		profileWave[sCnt].waveCfg2=(0<<7)|  //loopInf
															 (1-1);  //loopNum[6:0]
		profileWave[sCnt].powerCfg0 = rc8088_regCfg->ANA.CFG00.WORD; //run:1
		profileWave[sCnt].powerCfg1 = rc8088_regCfg->ANA.CFG00.WORD; //idle:0
		profileWave[sCnt].anaCfg0=rc8088_regCfg->ANA.CFG01.WORD;
		profileWave[sCnt].anaCfg1=rc8088_regCfg->ANA.CFG02.WORD;
		profileWave[sCnt].anaCfg2=rc8088_regCfg->ANA.CFG03.WORD;
		profileWave[sCnt].anaCfg3=rc8088_regCfg->ANA.CFG04.WORD;
		profileWave[sCnt].anaCfg4=rc8088_regCfg->ANA.CFG05.WORD;
		profileWave[sCnt].anaCfg5=rc8088_regCfg->ANA.CFG06.WORD;
		//profile lut ramp
		profileWave[sCnt].lutRampCfg0=(0<<24)|          //rampInterInc[7:0]
																	(0<<16)|          //rampIntraInc[3:0]
																	((profMemAddr.rampMemAddr-profMemAddr.profileAddr)&0xFFFF);  //rampBaseAddr[15:0]     offset,byte
		profileWave[sCnt].lutRampCfg1=(0<<8)|           //rampInterCnt[7:0]
									                (128-1);      //rampIntraCnt[7:0]
		profileWave[sCnt].lutRampCfg2=(0<<16)|          //deltaInterInc_ramp_a_time
									                (0);              //deltaInterInc_ramp_a_inc
		profileWave[sCnt].lutRampCfg3=(0<<16)|          //deltaInterInc_ramp_b_time
									                (0);              //deltaInterInc_ramp_b_inc
		profileWave[sCnt].lutRampCfg4=(0<<16)|          //deltaInterInc_ramp_c_time
									                (0);              //deltaInterInc_ramp_c_inc
		profileWave[sCnt].lutRampCfg5=(0<<16)|          //deltaIntraInc_ramp_a_time
									                (0);              //deltaIntraInc_ramp_a_inc
		profileWave[sCnt].lutRampCfg6=(0<<16)|          //deltaIntraInc_ramp_b_time
									                (0);              //deltaIntraInc_ramp_b_inc
		profileWave[sCnt].lutRampCfg7=(0<<16)|          //deltaIntraInc_ramp_c_time
									                (0);              //deltaIntraInc_ramp_c_inc
		//profile lut startFreq
		profileWave[sCnt].lutStartFreqCfg0=(0<<24)|           //startFreqInterInc[7:0]
										                   (0<<16)|           //startFreqIntraInc[3:0]
										                   ((profMemAddr.startFreqMemAddr-profMemAddr.profileAddr)&0xFFFF); //startFreqBaseAddr[15:0]
		profileWave[sCnt].lutStartFreqCfg1=(0<<8)|            //startFreqInterCnt[7:0]
										                   (0);               //startFreqIntraCnt[7:0]
		profileWave[sCnt].lutStartFreqCfg2=0;                 //deltaInterInc_startFreq
		profileWave[sCnt].lutStartFreqCfg3=0;                 //deltaIntraInc_startFreq
		//profile lut adcRma
		profileWave[sCnt].lutAdcRmaCfg0=(0<<24)|              //adcRmaInterInc[7:0]
										                (0<<16)|              //adcRmaIntraInc[3:0]
										                ((profMemAddr.adcRmaMemAddr-profMemAddr.profileAddr)&0xFFFF);    //adcRmaBaseAddr[15:0]
		profileWave[sCnt].lutAdcRmaCfg1=(0<<8)|               //adcRmaInterCnt[7:0]
										                (0);                  //adcRmaIntraCnt[7:0]
		profileWave[sCnt].lutAdcRmaCfg2=(0<<16)|              //deltaInterInc_adcRma
										                (0);                  //deltaIntraInc_adcRma
		//profile lut txEn
		profileWave[sCnt].lutTxEnCfg0=(0<<24)|                //txEnInterInc[7:0]
																  (0<<16)|                //txEnIntraInc[3:0]
																  ((profMemAddr.txEnMemAddr-profMemAddr.profileAddr)&0xFFFF);      //txEnBaseAddr[15:0]
		profileWave[sCnt].lutTxEnCfg1=(0<<8)|                 //txEnInterCnt[7:0]
																  (0);                    //txEnIntraCnt[7:0]
		//profile lut bpm
		profileWave[sCnt].lutBpmCfg0=(0<<24)|                 //bpmInterInc[7:0]
																 (0<<16)|                 //bpmIntraInc[3:0]
																 ((profMemAddr.bpmMemAddr-profMemAddr.profileAddr)&0xFFFF);       //bpmBaseAddr[15:0]
		profileWave[sCnt].lutBpmCfg1=(0<<8)|                  //bpmInterCnt[7:0]
									               (0);                     //bpmIntraCnt[7:0]
        #if TEST_TXPHASE_SHOW_EN
//            profileWave[sCnt].lutTx0PhaseCfg0=(0<<24)|(0<<16)|((profMemAddr.tx0PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
//            profileWave[sCnt].lutTx0PhaseCfg1=(0<<24)|(1<<16)|(0<<8)|(128-1);//deltaInterInc,deltaIntraInc,interCnt,intraCnt
            profileWave[sCnt].lutTx0PhaseCfg0=(0<<24)|(0<<16)|((profMemAddr.tx0PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
            profileWave[sCnt].lutTx0PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(8-1);//deltaInterInc,deltaIntraInc,interCnt,intraCnt
            //profile lut tx1 phase
            profileWave[sCnt].lutTx1PhaseCfg0=(0<<24)|(0<<16)|((profMemAddr.tx1PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
            profileWave[sCnt].lutTx1PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(8-1);//deltaInterInc,deltaIntraInc,interCnt,intraCnt
            //profile lut tx2 phase
            profileWave[sCnt].lutTx2PhaseCfg0=(0<<24)|(0<<16)|((profMemAddr.tx2PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
            profileWave[sCnt].lutTx2PhaseCfg1=(0<<24)|(16<<16)|(0<<8)|(8-1);//deltaInterInc,deltaIntraInc,interCnt,intraCnt
            //profile lut tx3 phase
            profileWave[sCnt].lutTx3PhaseCfg0=(0<<24)|(0<<16)|((profMemAddr.tx3PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
            profileWave[sCnt].lutTx3PhaseCfg1=(0<<24)|(32<<16)|(0<<8)|(8-1);//deltaInterInc,deltaIntraInc,interCnt,intraCnt
            //profile lut tx4 phase
            profileWave[sCnt].lutTx4PhaseCfg0=(0<<24)|(0<<16)|((profMemAddr.tx4PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
            profileWave[sCnt].lutTx4PhaseCfg1=(0<<24)|(48<<16)|(0<<8)|(8-1);//deltaInterInc,deltaIntraInc,interCnt,intraCnt
            //profile lut tx5 phase
            profileWave[sCnt].lutTx5PhaseCfg0=(0<<24)|(0<<16)|((profMemAddr.tx5PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
            profileWave[sCnt].lutTx5PhaseCfg1=(0<<24)|(64<<16)|(0<<8)|(8-1);//deltaInterInc,deltaIntraInc,interCnt,intraCnt
            //profile lut tx6 phase
            profileWave[sCnt].lutTx6PhaseCfg0=(0<<24)|(0<<16)|((profMemAddr.tx6PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
            profileWave[sCnt].lutTx6PhaseCfg1=(0<<24)|(80<<16)|(0<<8)|(8-1);//deltaInterInc,deltaIntraInc,interCnt,intraCnt
            //profile lut tx7 phase
            profileWave[sCnt].lutTx7PhaseCfg0=(0<<24)|(0<<16)|((profMemAddr.tx7PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
            profileWave[sCnt].lutTx7PhaseCfg1=(0<<24)|(0<<16)|(0<<8)|(1-1);//deltaInterInc,deltaIntraInc,interCnt,intraCnt        
        #else
            profileWave[sCnt].lutTx0PhaseCfg0=(0<<24)|(0<<16)|((profMemAddr.tx0PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
            profileWave[sCnt].lutTx0PhaseCfg1=(0<<24)|(deltaIntraInc_tx0Phase<<16)|(0<<8)|(128-1);//deltaInterInc,deltaIntraInc,interCnt,intraCnt
            //profile lut tx1 phase
            profileWave[sCnt].lutTx1PhaseCfg0=(0<<24)|(0<<16)|((profMemAddr.tx1PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
            profileWave[sCnt].lutTx1PhaseCfg1=(0<<24)|(deltaIntraInc_tx0Phase<<16)|(0<<8)|(128-1);//deltaInterInc,deltaIntraInc,interCnt,intraCnt
            //profile lut tx2 phase
            profileWave[sCnt].lutTx2PhaseCfg0=(0<<24)|(0<<16)|((profMemAddr.tx2PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
            profileWave[sCnt].lutTx2PhaseCfg1=(0<<24)|(deltaIntraInc_tx0Phase<<16)|(0<<8)|(128-1);//deltaInterInc,deltaIntraInc,interCnt,intraCnt
            //profile lut tx3 phase
            profileWave[sCnt].lutTx3PhaseCfg0=(0<<24)|(0<<16)|((profMemAddr.tx3PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
            profileWave[sCnt].lutTx3PhaseCfg1=(0<<24)|(deltaIntraInc_tx0Phase<<16)|(0<<8)|(128-1);//deltaInterInc,deltaIntraInc,interCnt,intraCnt
            //profile lut tx4 phase
            profileWave[sCnt].lutTx4PhaseCfg0=(0<<24)|(0<<16)|((profMemAddr.tx4PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
            profileWave[sCnt].lutTx4PhaseCfg1=(0<<24)|(deltaIntraInc_tx0Phase<<16)|(0<<8)|(128-1);//deltaInterInc,deltaIntraInc,interCnt,intraCnt
            //profile lut tx5 phase
            profileWave[sCnt].lutTx5PhaseCfg0=(0<<24)|(0<<16)|((profMemAddr.tx5PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
            profileWave[sCnt].lutTx5PhaseCfg1=(0<<24)|(deltaIntraInc_tx0Phase<<16)|(0<<8)|(128-1);//deltaInterInc,deltaIntraInc,interCnt,intraCnt
            //profile lut tx6 phase
            profileWave[sCnt].lutTx6PhaseCfg0=(0<<24)|(0<<16)|((profMemAddr.tx6PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
            profileWave[sCnt].lutTx6PhaseCfg1=(0<<24)|(deltaIntraInc_tx0Phase<<16)|(0<<8)|(128-1);//deltaInterInc,deltaIntraInc,interCnt,intraCnt
            //profile lut tx7 phase
            profileWave[sCnt].lutTx7PhaseCfg0=(0<<24)|(0<<16)|((profMemAddr.tx7PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
            profileWave[sCnt].lutTx7PhaseCfg1=(0<<24)|(deltaIntraInc_tx0Phase<<16)|(0<<8)|(128-1);//deltaInterInc,deltaIntraInc,interCnt,intraCnt
        #endif
        #if 0  //TX0 phaseStep = 64
		profileWave[sCnt].lutTx7PhaseCfg0=(0<<24)|(1<<16)|((profMemAddr.tx7PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
        profileWave[sCnt].lutTx7PhaseCfg1=(0<<24)|(deltaIntraInc_tx0Phase<<16)|(0<<8)|(2-1);//deltaInterInc,deltaIntraInc,interCnt,intraCnt
        #endif
	}
	/*write profileLut memory*/
	//ramp ABC
	uint32_t rampRst=0;
	/*10+25+50 1G*/   
	Write_M32(profMemAddr.rampMemAddr+0x00,(uint32_t)(40*10)<<16|((0)&0xFFFF)); //1000us
    rampRst=HAL_RC8088_CalcRampReg(1,25);//bandwidth,sweepTime
	Write_M32(profMemAddr.rampMemAddr+0x04,rampRst); //1000us
	rampRst=HAL_RC8088_CalcRampReg(-1,50);//bandwidth,sweepTime
	Write_M32(profMemAddr.rampMemAddr+0x08,rampRst); //1000us
	//startFreq
	Write_M32(profMemAddr.startFreqMemAddr,0x008A0000); //start freq  : 78G:0x008A0000
	//adcRma
	Write_M16(profMemAddr.adcRmaMemAddr+0,250);	
	//txEn
    #if TEST_TXPHASE_SHOW_EN
        Write_M8(profMemAddr.txEnMemAddr+0,1);//tx0-7	
    #else
        Write_M8(profMemAddr.txEnMemAddr+0,0x01);//tx0-7
    #endif
	//bpm
	Write_M8(profMemAddr.bpmMemAddr+0,0);//bpm
	//txPhase0:0
    Write_M8 (profMemAddr.tx0PhaseMemAddr+0,0);
    Write_M8 (profMemAddr.tx0PhaseMemAddr+1,0);
    Write_M8 (profMemAddr.tx0PhaseMemAddr+2,0);
    Write_M8 (profMemAddr.tx0PhaseMemAddr+3,0);
    Write_M8 (profMemAddr.tx0PhaseMemAddr+4,0);
    Write_M8 (profMemAddr.tx0PhaseMemAddr+5,0);
    Write_M8 (profMemAddr.tx0PhaseMemAddr+6,0);
    Write_M8 (profMemAddr.tx0PhaseMemAddr+7,0);
    //txPhase1:1/8
	Write_M8 (profMemAddr.tx1PhaseMemAddr+0,0  );
    Write_M8 (profMemAddr.tx1PhaseMemAddr+1,16 );
    Write_M8 (profMemAddr.tx1PhaseMemAddr+2,32 );
    Write_M8 (profMemAddr.tx1PhaseMemAddr+3,48 );
    Write_M8 (profMemAddr.tx1PhaseMemAddr+4,64 );
    Write_M8 (profMemAddr.tx1PhaseMemAddr+5,80 );
    Write_M8 (profMemAddr.tx1PhaseMemAddr+6,96 );
    Write_M8 (profMemAddr.tx1PhaseMemAddr+7,112);
    //txPhase2:2/8
	Write_M8 (profMemAddr.tx2PhaseMemAddr+0,0 );
    Write_M8 (profMemAddr.tx2PhaseMemAddr+1,32);
    Write_M8 (profMemAddr.tx2PhaseMemAddr+2,64);
    Write_M8 (profMemAddr.tx2PhaseMemAddr+3,96);
    Write_M8 (profMemAddr.tx2PhaseMemAddr+4,0 );
    Write_M8 (profMemAddr.tx2PhaseMemAddr+5,32);
    Write_M8 (profMemAddr.tx2PhaseMemAddr+6,64);
    Write_M8 (profMemAddr.tx2PhaseMemAddr+7,96);
    //txPhase3:3/8
    Write_M8 (profMemAddr.tx3PhaseMemAddr+0,0  );
    Write_M8 (profMemAddr.tx3PhaseMemAddr+1,48 );
    Write_M8 (profMemAddr.tx3PhaseMemAddr+2,96 );
    Write_M8 (profMemAddr.tx3PhaseMemAddr+3,16 );
    Write_M8 (profMemAddr.tx3PhaseMemAddr+4,64 );
    Write_M8 (profMemAddr.tx3PhaseMemAddr+5,112);
    Write_M8 (profMemAddr.tx3PhaseMemAddr+6,32 );
    Write_M8 (profMemAddr.tx3PhaseMemAddr+7,80 );
    //txPhase4:4/8
    Write_M8 (profMemAddr.tx4PhaseMemAddr+0,0 );
    Write_M8 (profMemAddr.tx4PhaseMemAddr+1,64);
    Write_M8 (profMemAddr.tx4PhaseMemAddr+2,0 );
    Write_M8 (profMemAddr.tx4PhaseMemAddr+3,64);
    Write_M8 (profMemAddr.tx4PhaseMemAddr+4,0 );
    Write_M8 (profMemAddr.tx4PhaseMemAddr+5,64);
    Write_M8 (profMemAddr.tx4PhaseMemAddr+6,0 );
    Write_M8 (profMemAddr.tx4PhaseMemAddr+7,64);
    //txPhase5:5/8
    Write_M8 (profMemAddr.tx5PhaseMemAddr+0,0  );
    Write_M8 (profMemAddr.tx5PhaseMemAddr+1,80 );
    Write_M8 (profMemAddr.tx5PhaseMemAddr+2,32 );
    Write_M8 (profMemAddr.tx5PhaseMemAddr+3,112);
    Write_M8 (profMemAddr.tx5PhaseMemAddr+4,64 );
    Write_M8 (profMemAddr.tx5PhaseMemAddr+5,16 );
    Write_M8 (profMemAddr.tx5PhaseMemAddr+6,96 );
    Write_M8 (profMemAddr.tx5PhaseMemAddr+7,48 );
    //txPhase6:6/8
    Write_M8 (profMemAddr.tx6PhaseMemAddr+0,0 );
    Write_M8 (profMemAddr.tx6PhaseMemAddr+1,96);
    Write_M8 (profMemAddr.tx6PhaseMemAddr+2,64);
    Write_M8 (profMemAddr.tx6PhaseMemAddr+3,32);
    Write_M8 (profMemAddr.tx6PhaseMemAddr+4,0 );
    Write_M8 (profMemAddr.tx6PhaseMemAddr+5,96);
    Write_M8 (profMemAddr.tx6PhaseMemAddr+6,64);
    Write_M8 (profMemAddr.tx6PhaseMemAddr+7,32);
    //txPhase7:7/8
    Write_M8 (profMemAddr.tx7PhaseMemAddr+0,0  );
    Write_M8 (profMemAddr.tx7PhaseMemAddr+1,112);
    Write_M8 (profMemAddr.tx7PhaseMemAddr+2,96 );
    Write_M8 (profMemAddr.tx7PhaseMemAddr+3,80 );
    Write_M8 (profMemAddr.tx7PhaseMemAddr+4,64 );
    Write_M8 (profMemAddr.tx7PhaseMemAddr+5,48 );
    Write_M8 (profMemAddr.tx7PhaseMemAddr+6,32 );
    Write_M8 (profMemAddr.tx7PhaseMemAddr+7,16 );

	HAL_RC8088_WrMem(&RC8088_RW, RC8088_CBUFF_BASE,rc8088_userCfg->userMemAddr.cBuf_Addr, 8192>>4);
	HAL_RC8088_RdMem(&RC8088_RW, RC8088_CBUFF_BASE, (RC8088_MemDat_st *)TEST_READ_MEM_ADDR, (8192)>>4);		
}

#endif
#if TEST_CALIB_WAVE_EN
/*
	QT generate need to config list :
	prep:numPT=512
	numRX:8
	profileMan:numChirp=256
	startFreq=78G
	bandwidth=0.8G
	MIPI: laneSpeed=800M
	
	QT sample need to config list:
	numFrame=1
	numChirp=256
	numPT=512
	numByte=2
	numRX=8
	
*/

void RC8088_ProfileLutCalibWaveConfig(void){
	STRUCT_PROFILELUT *profileWave=(STRUCT_PROFILELUT *)profMemAddr.profileAddr;
    memset((uint8_t *)TEST_WRITE_MEM_ADDR,0,16*128);
    HAL_RC8088_WrMem(&RC8088_RW, RC8088_TXBUFF_BASE, (RC8088_MemDat_st *)TEST_WRITE_MEM_ADDR, (16*128)>>4);//len:1=16Byte
    HAL_RC8088_RdMem(&RC8088_RW, RC8088_TXBUFF_BASE, (RC8088_MemDat_st *)TEST_READ_MEM_ADDR, (16*128)>>4);
	//config init
  rc8088_userCfg->numFrame=500;//numTX=8->128*8
	rc8088_userCfg->numProf = 2;
	rc8088_userCfg->adcRmaInitVal=250;
	rc8088_regCfg->PROFILE_MAN.ProfileMan_CFG0.BIT.profile_man_vld=0;
	HAL_RC8088_WrReg(&RC8088_RW, &rc8088_regCfg->PROFILE_MAN.ProfileMan_CFG0, 1);
	//subframe
	rc8088_regCfg->SF.SF_CFG0.BIT.sf0_profileLoopInf          =0;
	rc8088_regCfg->SF.SF_CFG0.BIT.sf0_profileLoopNum          =1-1;
	rc8088_regCfg->SF.SF_CFG0.BIT.sf0_profileNumA             =0;
	rc8088_regCfg->SF.SF_CFG0.BIT.sf0_profileNumB             =1;
	rc8088_regCfg->SF.SF_CFG0.BIT.sf0_interFrameIdleTimeScaleB=0;
	rc8088_regCfg->SF.SF_CFG0.BIT.sf0_interFrameIdleTimeValueB=0;
	HAL_RC8088_WrReg(&RC8088_RW, &rc8088_regCfg->SF.SF_CFG0, 1);
	//write profile addr
    uint32_t deltaIntraInc_tx0Phase=0;//0,1,16,32,48
	
  for (uint32_t sCnt=0;sCnt<rc8088_userCfg->numProf;sCnt++){
		profileWave[sCnt].waveCfg0=(0<<12)| //ramp_rma
															 (0<<10)| //A_PLLACC
															 (0<<9)|  //B_PLLACC
															 (0<<8)|  //C_PLLACC
															 (1<<6)|  //A_PAenable
															 (1<<5)|  //B_PAenable
															 (0<<4)|  //C_PAenable
															 (1<<2)|  //ramp_sync_maskA
															 (0<<1)|  //ramp_sync_maskB
															 (0);     //ramp_sync_maskC
		profileWave[sCnt].waveCfg1=(0<<4)|  //interProfileIdleTimeScaleB
															 (0);     //interProfileIdleTimeValueB
		profileWave[sCnt].waveCfg2=(0<<7)|  //loopInf
															 (1-1);  //loopNum[6:0]
		profileWave[sCnt].powerCfg0 = rc8088_regCfg->ANA.CFG00.WORD; //run:1
		profileWave[sCnt].powerCfg1 = rc8088_regCfg->ANA.CFG00.WORD; //idle:0
		profileWave[sCnt].anaCfg0=rc8088_regCfg->ANA.CFG01.WORD;
		profileWave[sCnt].anaCfg1=rc8088_regCfg->ANA.CFG02.WORD;
		profileWave[sCnt].anaCfg2=rc8088_regCfg->ANA.CFG03.WORD;
		profileWave[sCnt].anaCfg3=rc8088_regCfg->ANA.CFG04.WORD;
		profileWave[sCnt].anaCfg4=rc8088_regCfg->ANA.CFG05.WORD;
		profileWave[sCnt].anaCfg5=rc8088_regCfg->ANA.CFG06.WORD;
		//profile lut ramp
		profileWave[sCnt].lutRampCfg0=(0<<24)|          //rampInterInc[7:0]
																	(0<<16)|          //rampIntraInc[3:0]
																	((profMemAddr.rampMemAddr-profMemAddr.profileAddr)&0xFFFF);  //rampBaseAddr[15:0]     offset,byte
		profileWave[sCnt].lutRampCfg1=(0<<8)|           //rampInterCnt[7:0]
									                (rc8088_userCfg->numChirp-1);      //rampIntraCnt[7:0]
		profileWave[sCnt].lutRampCfg2=(0<<16)|          //deltaInterInc_ramp_a_time
									                (0);              //deltaInterInc_ramp_a_inc
		profileWave[sCnt].lutRampCfg3=(0<<16)|          //deltaInterInc_ramp_b_time
									                (0);              //deltaInterInc_ramp_b_inc
		profileWave[sCnt].lutRampCfg4=(0<<16)|          //deltaInterInc_ramp_c_time
									                (0);              //deltaInterInc_ramp_c_inc
		profileWave[sCnt].lutRampCfg5=(0<<16)|          //deltaIntraInc_ramp_a_time
									                (0);              //deltaIntraInc_ramp_a_inc
		profileWave[sCnt].lutRampCfg6=(0<<16)|          //deltaIntraInc_ramp_b_time
									                (0);              //deltaIntraInc_ramp_b_inc
		profileWave[sCnt].lutRampCfg7=(0<<16)|          //deltaIntraInc_ramp_c_time
									                (0);              //deltaIntraInc_ramp_c_inc
		//profile lut startFreq
		profileWave[sCnt].lutStartFreqCfg0=(0<<24)|           //startFreqInterInc[7:0]
										                   (0<<16)|           //startFreqIntraInc[3:0]
										                   ((profMemAddr.startFreqMemAddr-profMemAddr.profileAddr)&0xFFFF); //startFreqBaseAddr[15:0]
		profileWave[sCnt].lutStartFreqCfg1=(0<<8)|            //startFreqInterCnt[7:0]
										                   (0);               //startFreqIntraCnt[7:0]
		profileWave[sCnt].lutStartFreqCfg2=0;                 //deltaInterInc_startFreq
		profileWave[sCnt].lutStartFreqCfg3=0;                 //deltaIntraInc_startFreq
		//profile lut adcRma
		profileWave[sCnt].lutAdcRmaCfg0=(0<<24)|              //adcRmaInterInc[7:0]
										                (0<<16)|              //adcRmaIntraInc[3:0]
										                ((profMemAddr.adcRmaMemAddr-profMemAddr.profileAddr)&0xFFFF);    //adcRmaBaseAddr[15:0]
		profileWave[sCnt].lutAdcRmaCfg1=(0<<8)|               //adcRmaInterCnt[7:0]
										                (0);                  //adcRmaIntraCnt[7:0]
		profileWave[sCnt].lutAdcRmaCfg2=(0<<16)|              //deltaInterInc_adcRma
										                (0);                  //deltaIntraInc_adcRma
		//profile lut txEn
		profileWave[sCnt].lutTxEnCfg0=(0<<24)|                //txEnInterInc[7:0]
																  (0<<16)|                //txEnIntraInc[3:0]
																  ((profMemAddr.txEnMemAddr-profMemAddr.profileAddr)&0xFFFF);      //txEnBaseAddr[15:0]
		profileWave[sCnt].lutTxEnCfg1=(0<<8)|                 //txEnInterCnt[7:0]
																  (0);                    //txEnIntraCnt[7:0]
		//profile lut bpm
		profileWave[sCnt].lutBpmCfg0=(0<<24)|                 //bpmInterInc[7:0]
																 (0<<16)|                 //bpmIntraInc[3:0]
																 ((profMemAddr.bpmMemAddr-profMemAddr.profileAddr)&0xFFFF);       //bpmBaseAddr[15:0]
		profileWave[sCnt].lutBpmCfg1=(0<<8)|                  //bpmInterCnt[7:0]
									               (0);                     //bpmIntraCnt[7:0]
        profileWave[sCnt].lutTx0PhaseCfg0=(0<<24)|(0<<16)|((profMemAddr.tx0PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
        profileWave[sCnt].lutTx0PhaseCfg1=(0<<24)|(deltaIntraInc_tx0Phase<<16)|(0<<8)|(1-1);//deltaInterInc,deltaIntraInc,interCnt,intraCnt
        //profile lut tx1 phase
        profileWave[sCnt].lutTx1PhaseCfg0=(0<<24)|(0<<16)|((profMemAddr.tx1PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
        profileWave[sCnt].lutTx1PhaseCfg1=(0<<24)|(deltaIntraInc_tx0Phase<<16)|(0<<8)|(1-1);//deltaInterInc,deltaIntraInc,interCnt,intraCnt
        //profile lut tx2 phase
        profileWave[sCnt].lutTx2PhaseCfg0=(0<<24)|(0<<16)|((profMemAddr.tx2PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
        profileWave[sCnt].lutTx2PhaseCfg1=(0<<24)|(deltaIntraInc_tx0Phase<<16)|(0<<8)|(1-1);//deltaInterInc,deltaIntraInc,interCnt,intraCnt
        //profile lut tx3 phase
        profileWave[sCnt].lutTx3PhaseCfg0=(0<<24)|(0<<16)|((profMemAddr.tx3PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
        profileWave[sCnt].lutTx3PhaseCfg1=(0<<24)|(deltaIntraInc_tx0Phase<<16)|(0<<8)|(1-1);//deltaInterInc,deltaIntraInc,interCnt,intraCnt
        //profile lut tx4 phase
        profileWave[sCnt].lutTx4PhaseCfg0=(0<<24)|(0<<16)|((profMemAddr.tx4PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
        profileWave[sCnt].lutTx4PhaseCfg1=(0<<24)|(deltaIntraInc_tx0Phase<<16)|(0<<8)|(1-1);//deltaInterInc,deltaIntraInc,interCnt,intraCnt
        //profile lut tx5 phase
        profileWave[sCnt].lutTx5PhaseCfg0=(0<<24)|(0<<16)|((profMemAddr.tx5PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
        profileWave[sCnt].lutTx5PhaseCfg1=(0<<24)|(deltaIntraInc_tx0Phase<<16)|(0<<8)|(1-1);//deltaInterInc,deltaIntraInc,interCnt,intraCnt
        //profile lut tx6 phase
        profileWave[sCnt].lutTx6PhaseCfg0=(0<<24)|(0<<16)|((profMemAddr.tx6PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
        profileWave[sCnt].lutTx6PhaseCfg1=(0<<24)|(deltaIntraInc_tx0Phase<<16)|(0<<8)|(1-1);//deltaInterInc,deltaIntraInc,interCnt,intraCnt
        //profile lut tx7 phase
        profileWave[sCnt].lutTx7PhaseCfg0=(0<<24)|(0<<16)|((profMemAddr.tx7PhaseMemAddr-profMemAddr.profileAddr)&0xFFFF);//interInc,intraInc,baseAddr
        profileWave[sCnt].lutTx7PhaseCfg1=(0<<24)|(deltaIntraInc_tx0Phase<<16)|(0<<8)|(1-1);//deltaInterInc,deltaIntraInc,interCnt,intraCnt
	}
	/*write profileLut memory*/
	//ramp ABC
	uint32_t rampRst=0;
    /*1000+1000+1000 0G*/
    Write_M32(profMemAddr.rampMemAddr+0x00,(uint32_t)(40*1000)<<16|((0)&0xFFFF)); //1000us
    Write_M32(profMemAddr.rampMemAddr+0x04,(uint32_t)(40*1000)<<16|((0)&0xFFFF)); //1000us
    Write_M32(profMemAddr.rampMemAddr+0x08,(uint32_t)(40*1000)<<16|((0)&0xFFFF)); //1000us
//    /*10+15+50 0.8G*/
    Write_M32(profMemAddr.rampMemAddr+0x0C,(40*10)<<16|((0)&0xFFFF)); //10us
    rampRst=HAL_RC8088_CalcRampReg(0.8,15);
    Write_M32(profMemAddr.rampMemAddr+0x10,(rampRst<<16)|((rampRst>>16)&0xFFFF)); //15us@0.8G
    rampRst=HAL_RC8088_CalcRampReg(0.8,50);
    Write_M32(profMemAddr.rampMemAddr+0x14,(uint32_t)(rampRst<<16)|((0x10000-(rampRst>>16))&0xFFFF)); //50us@-0.8G
    /*10+15+50 3G*/
//    Write_M32(profMemAddr.rampMemAddr+0x0C,(40*10)<<16|((0)&0xFFFF)); //10us
//    rampRst=HAL_RC8088_CalcRampReg(3,15);
//    Write_M32(profMemAddr.rampMemAddr+0x10,(rampRst<<16)|((rampRst>>16)&0xFFFF)); //15us@0.8G
//    rampRst=HAL_RC8088_CalcRampReg(3,50);
//    Write_M32(profMemAddr.rampMemAddr+0x14,(uint32_t)(rampRst<<16)|((0x10000-(rampRst>>16))&0xFFFF)); //50us@-0.8G
	//startFreq
	Write_M32(profMemAddr.startFreqMemAddr,0x00BCBCA1); //start freq  : 78G:0x00BCBCA1
	//adcRma
	Write_M16(profMemAddr.adcRmaMemAddr+0,rc8088_userCfg->adcRmaInitVal);	
	//txEn
    Write_M8(profMemAddr.txEnMemAddr+0,0x01);//tx0-7	
    Write_M8(profMemAddr.txEnMemAddr+1,0x02);//tx0-7
    Write_M8(profMemAddr.txEnMemAddr+2,0x04);//tx0-7
    Write_M8(profMemAddr.txEnMemAddr+3,0x08);//tx0-7
    Write_M8(profMemAddr.txEnMemAddr+4,0x10);//tx0-7
    Write_M8(profMemAddr.txEnMemAddr+5,0x20);//tx0-7
    Write_M8(profMemAddr.txEnMemAddr+6,0x40);//tx0-7
    Write_M8(profMemAddr.txEnMemAddr+7,0x80);//tx0-7
	//bpm
	Write_M8(profMemAddr.bpmMemAddr+0,0);//bpm
	//txPhase0:0
    Write_M8 (profMemAddr.tx0PhaseMemAddr+0,0);
    Write_M8 (profMemAddr.tx1PhaseMemAddr+0,0);
    Write_M8 (profMemAddr.tx2PhaseMemAddr+0,0);
    Write_M8 (profMemAddr.tx3PhaseMemAddr+0,0);
    Write_M8 (profMemAddr.tx4PhaseMemAddr+0,0);
    Write_M8 (profMemAddr.tx5PhaseMemAddr+0,0);
    Write_M8 (profMemAddr.tx6PhaseMemAddr+0,0);
    Write_M8 (profMemAddr.tx7PhaseMemAddr+0,0);
    //config special profileLut
    //profile0
	profileWave[0].waveCfg0=(0<<12)| //ramp_rma
                            (0<<10)| //A_PLLACC
                            (0<<9)|  //B_PLLACC
                            (0<<8)|  //C_PLLACC
                            (1<<6)|  //A_PAenable
                            (1<<5)|  //B_PAenable
                            (0<<4)|  //C_PAenable
                            (1<<2)|  //ramp_sync_maskA
                            (1<<1)|  //ramp_sync_maskB
                            (1);     //ramp_sync_maskC	
	profileWave[0].lutRampCfg0=(0<<24)|          //rampInterInc[7:0]
							   (1<<16)|          //rampIntraInc[3:0]
							   ((profMemAddr.rampMemAddr-profMemAddr.profileAddr)&0xFFFF);  //rampBaseAddr[15:0]     offset,byte
	profileWave[0].lutRampCfg1=(0<<8)|(2-1);     //rampInterCnt[7:0]  //rampIntraCnt[7:0]
    //profile1: 78G 10+15+50   0.8G
    profileWave[1].lutRampCfg0=(0<<24)|          //rampInterInc[7:0]
                               (0<<16)|          //rampIntraInc[3:0]
                               ((profMemAddr.rampMemAddr-profMemAddr.profileAddr+0x0C)&0xFFFF);  //rampBaseAddr[15:0]     offset,byte
    profileWave[1].lutRampCfg1=(((rc8088_userCfg->numChirp>>3)-1)<<8)|           //rampInterCnt[7:0]
                               (8-1);      //rampIntraCnt[7:0]
    profileWave[1].lutTxEnCfg0=(0<<24)|                //txEnInterInc[7:0]
                               (1<<16)|                //txEnIntraInc[3:0]
                               ((profMemAddr.txEnMemAddr-profMemAddr.profileAddr)&0xFFFF);      //txEnBaseAddr[15:0]
    profileWave[1].lutTxEnCfg1=(0<<8)|                 //txEnInterCnt[7:0]
                               (8-1);                    //txEnIntraCnt[7:0]
    HAL_RC8088_WrMem(&RC8088_RW, RC8088_CBUFF_BASE,rc8088_userCfg->userMemAddr.cBuf_Addr, 8192>>4);
	HAL_RC8088_RdMem(&RC8088_RW, RC8088_CBUFF_BASE, (RC8088_MemDat_st *)TEST_READ_MEM_ADDR, (8192)>>4);		
}
#endif











